Commit cc4d07a4 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-imx-4.17-misc' of... 

Merge tag 'clk-imx-4.17-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx

Pull i.MX clock misc updates from Shawn Guo:

 - A correction on i.MX6SX CKO clock mux options.
 - A fix on i.MX7D Video PLL clock tree to include the missing dividers.
 - Update i.MX6UL/ULL clock driver to add epdc_podf instead of sim_podf
   clock for i.MX6ULL.

* tag 'clk-imx-4.17-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx6ull: Add epdc_podf instead of sim_podf
  clk: imx: imx7d: correct video pll clock tree
  clk: imx: imx6sx: update cko mux options
parents 84b7bbac a5510399

drivers/clk/imx/clk-imx6sx.c

+7 −7
Original line number Diff line number Diff line
@@ -63,17 +63,17 @@ static const char *lcdif2_sels[] = { "lcdif2_podf", "ipp_di0", "ipp_di1", "ldb_d 
static const char *display_sels[]	= { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", };

static const char *csi_sels[]		= { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };

static const char *cko1_sels[]		= {

	"pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",

	"dummy", "ocram", "dummy", "pxp_axi", "epdc_axi", "lcdif_pix",

	"epdc_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",

	"dummy", "dummy", "dummy", "dummy",

	"vadc", "ocram", "qspi2", "m4", "enet_ahb", "lcdif2_pix",

	"lcdif1_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",

};

static const char *cko2_sels[]		= {

	"dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck",

	"ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",

	"lcdif_axi", "dummy", "osc", "dummy", "gpu2d_ovg_core",

	"usdhc2", "ssi1", "ssi2", "ssi3", "gpu2d_core", "dummy",

	"dummy", "dummy", "dummy", "esai_extal", "eim_slow", "uart_serial",

	"spdif", "asrc", "dummy",

	"display_axi", "dummy", "osc", "dummy", "dummy",

	"usdhc2", "ssi1", "ssi2", "ssi3", "gpu_axi_podf", "dummy",

	"can_podf", "lvds1_out", "qspi1", "esai_extal", "eim_slow",

	"uart_serial", "spdif", "audio", "dummy",

};

static const char *cko_sels[] = { "cko1", "cko2", };

static const char *lvds_sels[]	= {

drivers/clk/imx/clk-imx6ul.c

+4 −1
Original line number Diff line number Diff line
@@ -308,7 +308,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clks[IMX6UL_CLK_SAI2_PODF]	= imx_clk_divider("sai2_podf",	   "sai2_pred",		base + 0x2c, 0,  6);

	clks[IMX6UL_CLK_SPDIF_PRED]	= imx_clk_divider("spdif_pred",	   "spdif_sel",		base + 0x30, 25, 3);

	clks[IMX6UL_CLK_SPDIF_PODF]	= imx_clk_divider("spdif_podf",	   "spdif_pred",	base + 0x30, 22, 3);

	if (clk_on_imx6ul())

		clks[IMX6UL_CLK_SIM_PODF]	= imx_clk_divider("sim_podf",	   "sim_pre_sel",	base + 0x34, 12, 3);

	else if (clk_on_imx6ull())

		clks[IMX6ULL_CLK_EPDC_PODF]	= imx_clk_divider("epdc_podf",	   "epdc_pre_sel",	base + 0x34, 12, 3);

	clks[IMX6UL_CLK_ECSPI_PODF]	= imx_clk_divider("ecspi_podf",	   "ecspi_sel",		base + 0x38, 19, 6);

	clks[IMX6UL_CLK_LCDIF_PRED]	= imx_clk_divider("lcdif_pred",	   "lcdif_pre_sel",	base + 0x38, 12, 3);

	clks[IMX6UL_CLK_CSI_PODF]       = imx_clk_divider("csi_podf",      "csi_sel",           base + 0x3c, 11, 3);

drivers/clk/imx/clk-imx7d.c

+44 −40
Original line number Diff line number Diff line
@@ -51,20 +51,20 @@ static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk", 


static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",

	"pll_enet_250m_clk", "pll_sys_pfd2_270m_clk",

	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",

	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",

	"pll_usb_main_clk", };



static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",

	"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk",

	"pll_audio_post_div", "pll_video_main_clk", "pll_sys_pfd7_clk", };

	"pll_audio_post_div", "pll_video_post_div", "pll_sys_pfd7_clk", };



static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",

	"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk",

	"pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_main_clk", };

	"pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_post_div", };



static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk",

	"pll_dram_533m_clk", "pll_enet_250m_clk",

	"pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_main_clk",

	"pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_post_div",

	"pll_sys_pfd4_clk", };



static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
@@ -75,7 +75,7 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", 
static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",

	"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",

	"pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div",

	"pll_video_main_clk", };

	"pll_video_post_div", };



static const char *dram_phym_sel[] = { "pll_dram_main_clk",

	"dram_phym_alt_clk", };
@@ -86,7 +86,7 @@ static const char *dram_sel[] = { "pll_dram_main_clk", 
static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",

	"pll_sys_main_clk", "pll_enet_500m_clk",

	"pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div",

	"pll_video_main_clk", };

	"pll_video_post_div", };



static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk",

	"pll_sys_main_clk", "pll_enet_500m_clk",
@@ -108,62 +108,62 @@ static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk", 


static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk",

	"pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk",

	"pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_main_clk", };

	"pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_post_div", };



static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk",

	"pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk",

	"pll_sys_pfd2_270m_clk", "pll_video_main_clk",

	"pll_sys_pfd2_270m_clk", "pll_video_post_div",

	"pll_usb_main_clk", };



static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk",

	"pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",

	"pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", };

	"pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };



static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk",

	"pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",

	"pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", };

	"pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };



static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk",

	"pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2",

	"pll_video_main_clk", "ext_clk_3", };

	"pll_video_post_div", "ext_clk_3", };



static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",

	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",

	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",

	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };



static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",

	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",

	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",

	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };



static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk",

	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",

	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",

	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", };



static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk",

	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",

	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",

	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", };



static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk",

	"pll_enet_50m_clk", "pll_enet_25m_clk",

	"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk",

	"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",

	"ext_clk_4", };



static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",

	"ext_clk_4", "pll_video_main_clk", };

	"ext_clk_4", "pll_video_post_div", };



static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk",

	"pll_enet_50m_clk", "pll_enet_25m_clk",

	"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk",

	"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",

	"ext_clk_4", };



static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",

	"ext_clk_4", "pll_video_main_clk", };

	"ext_clk_4", "pll_video_post_div", };



static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk",

	"pll_enet_50m_clk", "pll_enet_125m_clk",

	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",

	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",

	"pll_sys_pfd3_clk", };



static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
@@ -174,7 +174,7 @@ static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 
static const char *nand_sel[] = { "osc", "pll_sys_main_clk",

	"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk",

	"pll_enet_500m_clk", "pll_enet_250m_clk",

	"pll_video_main_clk", };

	"pll_video_post_div", };



static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk",

	"pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk",
@@ -204,22 +204,22 @@ static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk", 


static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk",

	"pll_enet_50m_clk", "pll_dram_533m_clk",

	"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",

	"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",

	"pll_sys_pfd2_135m_clk", };



static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk",

	"pll_enet_50m_clk", "pll_dram_533m_clk",

	"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",

	"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",

	"pll_sys_pfd2_135m_clk", };



static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk",

	"pll_enet_50m_clk", "pll_dram_533m_clk",

	"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",

	"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",

	"pll_sys_pfd2_135m_clk", };



static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk",

	"pll_enet_50m_clk", "pll_dram_533m_clk",

	"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",

	"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",

	"pll_sys_pfd2_135m_clk", };



static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk",
@@ -279,27 +279,27 @@ static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk", 


static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",

	"ext_clk_1", "ref_1m_clk", "pll_video_main_clk", };

	"ext_clk_1", "ref_1m_clk", "pll_video_post_div", };



static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",

	"ext_clk_1", "ref_1m_clk", "pll_video_main_clk", };

	"ext_clk_1", "ref_1m_clk", "pll_video_post_div", };



static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",

	"ext_clk_2", "ref_1m_clk", "pll_video_main_clk", };

	"ext_clk_2", "ref_1m_clk", "pll_video_post_div", };



static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",

	"ext_clk_2", "ref_1m_clk", "pll_video_main_clk", };

	"ext_clk_2", "ref_1m_clk", "pll_video_post_div", };



static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",

	"ext_clk_3", "ref_1m_clk", "pll_video_main_clk", };

	"ext_clk_3", "ref_1m_clk", "pll_video_post_div", };



static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",

	"ext_clk_3", "ref_1m_clk", "pll_video_main_clk", };

	"ext_clk_3", "ref_1m_clk", "pll_video_post_div", };



static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",

	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
@@ -308,23 +308,23 @@ static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 


static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",

	"pll_sys_main_120m_clk", "pll_dram_533m_clk",

	"pll_usb_main_clk", "pll_video_main_clk", "pll_enet_125m_clk",

	"pll_usb_main_clk", "pll_video_post_div", "pll_enet_125m_clk",

	"pll_sys_pfd7_clk", };



static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",

	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",

	"ref_1m_clk", "pll_audio_post_div", "ext_clk_1", };



static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",

	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",

	"ref_1m_clk", "pll_audio_post_div", "ext_clk_2", };



static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",

	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",

	"ref_1m_clk", "pll_audio_post_div", "ext_clk_3", };



static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk",

	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",

	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",

	"ref_1m_clk", "pll_audio_post_div", "ext_clk_4", };



static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
@@ -339,12 +339,12 @@ static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 


static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",

	"pll_sys_main_120m_clk", "pll_dram_533m_clk",

	"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk",

	"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",

	"pll_usb_main_clk", };



static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",

	"pll_sys_main_120m_clk", "pll_dram_533m_clk",

	"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk",

	"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",

	"pll_usb_main_clk", };



static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk",
@@ -358,13 +358,13 @@ static const char *clko1_sel[] = { "osc", "pll_sys_main_clk", 


static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk",

	"pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk",

	"pll_audio_post_div", "pll_video_main_clk", "ckil", };

	"pll_audio_post_div", "pll_video_post_div", "ckil", };



static const char *lvds1_sel[] = { "pll_arm_main_clk",

	"pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk",

	"pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",

	"pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk",

	"pll_audio_post_div", "pll_video_main_clk", "pll_enet_500m_clk",

	"pll_audio_post_div", "pll_video_post_div", "pll_enet_500m_clk",

	"pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk",

	"pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk",

	"pll_dram_main_clk", };
@@ -450,6 +450,10 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) 
				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock);

	clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div",

				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock);

	clks[IMX7D_PLL_VIDEO_TEST_DIV]  = clk_register_divider_table(NULL, "pll_video_test_div", "pll_video_main_clk",

				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 19, 2, 0, test_div_table, &imx_ccm_lock);

	clks[IMX7D_PLL_VIDEO_POST_DIV] = clk_register_divider_table(NULL, "pll_video_post_div", "pll_video_test_div",

				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock);



	clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0);

	clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1);

CRA Git | Maintained and supported by SUSTech CRA and CCSE