Commit cc38cae7 authored by Oscar Mateo's avatar Oscar Mateo Committed by Mika Kuoppala
Browse files

drm/i915/icl: Introduce initial Icelake Workarounds 



Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
    comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
      drm/i915/icl: add icelake_init_clock_gating()
    from Paulo Zanoni <paulo.r.zanoni@intel.com>
  - Squashed with this patch:
      drm/i915/icl: WaForceEnableNonCoherent
    from Oscar Mateo <oscar.mateo@intel.com>
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
    applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
    to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck
v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
v9:
  - C, not lisp (Chris)
  - WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko)

Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-2-git-send-email-oscar.mateo@intel.com
parent ca6acc25

drivers/gpu/drm/i915/i915_drv.h

+9 −0
Original line number Diff line number Diff line
@@ -2470,6 +2470,15 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define IS_CNL_REVID(p, since, until) \

	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))



#define ICL_REVID_A0		0x0

#define ICL_REVID_A2		0x1

#define ICL_REVID_B0		0x3

#define ICL_REVID_B2		0x4

#define ICL_REVID_C0		0x5



#define IS_ICL_REVID(p, since, until) \

	(IS_ICELAKE(p) && IS_REVID(p, since, until))



/*

 * The genX designation typically refers to the render engine, so render

 * capability related checks should use IS_GEN, while display and other checks

drivers/gpu/drm/i915/i915_gem_gtt.c

+3 −3
Original line number Diff line number Diff line
@@ -2138,15 +2138,15 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) 
	 * called on driver load and after a GPU reset, so you can place

	 * workarounds here even if they get overwritten by GPU reset.

	 */

	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */

	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */

	if (IS_BROADWELL(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);

	else if (IS_CHERRYVIEW(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);

	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);

	else if (IS_GEN9_LP(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);

	else if (INTEL_GEN(dev_priv) >= 9)

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);



	/*

	 * To support 64K PTEs we need to first enable the use of the

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -7238,6 +7238,7 @@ enum { 
/* GEN8 chicken */

#define HDC_CHICKEN0				_MMIO(0x7300)

#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)

#define ICL_HDC_MODE				_MMIO(0xE5F4)

#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)

#define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)

#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)

drivers/gpu/drm/i915/intel_lrc.c

+2 −0
Original line number Diff line number Diff line
@@ -1682,6 +1682,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) 
		return -EINVAL;



	switch (INTEL_GEN(engine->i915)) {

	case 11:

		return 0;

	case 10:

		wa_bb_fn[0] = gen10_init_indirectctx_bb;

		wa_bb_fn[1] = NULL;

drivers/gpu/drm/i915/intel_pm.c

+3 −1
Original line number Diff line number Diff line
@@ -9190,7 +9190,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) 
 */

void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)

{

	if (IS_CANNONLAKE(dev_priv))

	if (IS_ICELAKE(dev_priv))

		dev_priv->display.init_clock_gating = nop_init_clock_gating;

	else if (IS_CANNONLAKE(dev_priv))

		dev_priv->display.init_clock_gating = cnl_init_clock_gating;

	else if (IS_COFFEELAKE(dev_priv))

		dev_priv->display.init_clock_gating = cfl_init_clock_gating;

CRA Git | Maintained and supported by SUSTech CRA and CCSE