clk: stratix10: use do_div() for 64-bit calculation (cc26ed7b) · Commits · 戴 / test

do_div() macro to perform u64 division and guards against overflow if the result is too large for the unsigned long return type. Signed-off-by:

drivers/clk/socfpga/clk-pll-s10.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -39,7 +39,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
		/* read VCO1 reg for numerator and denominator */
		reg = readl(socfpgaclk->hw.reg);
		refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
		vco_freq = (unsigned long long)parent_rate / refdiv;

		vco_freq = parent_rate;
		do_div(vco_freq, refdiv);

		/* Read mdiv and fdiv from the fdbck register */
		reg = readl(socfpgaclk->hw.reg + 0x4);