Commit cc089e8a authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Don't pass crtc to intel_get_shared_dpll() and .get_dpll() 



Passing both crtc and its state is redundant. Pass just the state.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-2-ville.syrjala@linux.intel.com


Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent da373907

drivers/gpu/drm/i915/intel_display.c

+2 −2
Original line number Diff line number Diff line
@@ -9007,7 +9007,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, 


	ironlake_compute_dpll(crtc, crtc_state, NULL);



	if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {

	if (!intel_get_shared_dpll(crtc_state, NULL)) {

		DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",

			      pipe_name(crtc->pipe));

		return -EINVAL;
@@ -9608,7 +9608,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc, 
		struct intel_encoder *encoder =

			intel_get_crtc_new_encoder(state, crtc_state);



		if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {

		if (!intel_get_shared_dpll(crtc_state, encoder)) {

			DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",

				      pipe_name(crtc->pipe));

			return -EINVAL;

drivers/gpu/drm/i915/intel_dpll_mgr.c

+27 −29
Original line number Diff line number Diff line
@@ -420,9 +420,10 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, 
}



static struct intel_shared_dpll *

ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,

ibx_get_dpll(struct intel_crtc_state *crtc_state,

	     struct intel_encoder *encoder)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_shared_dpll *pll;

	enum intel_dpll_id i;
@@ -764,15 +765,13 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, 
	*r2_out = best.r2;

}



static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock,

						       struct intel_crtc *crtc,

						       struct intel_crtc_state *crtc_state)

static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(struct intel_crtc_state *crtc_state)

{

	struct intel_shared_dpll *pll;

	u32 val;

	unsigned int p, n2, r2;



	hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);

	hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);



	val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |

	      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
@@ -790,11 +789,12 @@ static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock, 
}



static struct intel_shared_dpll *

hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, int clock)

hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

	struct intel_shared_dpll *pll;

	enum intel_dpll_id pll_id;

	int clock = crtc_state->port_clock;



	switch (clock / 2) {

	case 81000:
@@ -820,19 +820,18 @@ hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, int clock) 
}



static struct intel_shared_dpll *

hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,

hsw_get_dpll(struct intel_crtc_state *crtc_state,

	     struct intel_encoder *encoder)

{

	struct intel_shared_dpll *pll;

	int clock = crtc_state->port_clock;



	memset(&crtc_state->dpll_hw_state, 0,

	       sizeof(crtc_state->dpll_hw_state));



	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

		pll = hsw_ddi_hdmi_get_dpll(clock, crtc, crtc_state);

		pll = hsw_ddi_hdmi_get_dpll(crtc_state);

	} else if (intel_crtc_has_dp_encoder(crtc_state)) {

		pll = hsw_ddi_dp_get_dpll(encoder, clock);

		pll = hsw_ddi_dp_get_dpll(crtc_state);

	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {

		if (WARN_ON(crtc_state->port_clock / 2 != 135000))

			return NULL;
@@ -1383,9 +1382,10 @@ skl_ddi_dp_set_dpll_hw_state(int clock, 
}



static struct intel_shared_dpll *

skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,

skl_get_dpll(struct intel_crtc_state *crtc_state,

	     struct intel_encoder *encoder)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct intel_shared_dpll *pll;

	int clock = crtc_state->port_clock;

	bool bret;
@@ -1827,10 +1827,10 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc *intel_crtc, 
}



static struct intel_shared_dpll *

bxt_get_dpll(struct intel_crtc *crtc,

		struct intel_crtc_state *crtc_state,

bxt_get_dpll(struct intel_crtc_state *crtc_state,

	     struct intel_encoder *encoder)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct intel_dpll_hw_state dpll_hw_state = { };

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_shared_dpll *pll;
@@ -1911,8 +1911,7 @@ static void intel_ddi_pll_init(struct drm_device *dev) 
struct intel_dpll_mgr {

	const struct dpll_info *dpll_info;



	struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc,

					      struct intel_crtc_state *crtc_state,

	struct intel_shared_dpll *(*get_dpll)(struct intel_crtc_state *crtc_state,

					      struct intel_encoder *encoder);



	void (*dump_hw_state)(struct drm_i915_private *dev_priv,
@@ -2361,9 +2360,10 @@ cnl_ddi_dp_set_dpll_hw_state(int clock, 
}



static struct intel_shared_dpll *

cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,

cnl_get_dpll(struct intel_crtc_state *crtc_state,

	     struct intel_encoder *encoder)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct intel_shared_dpll *pll;

	int clock = crtc_state->port_clock;

	bool bret;
@@ -2887,10 +2887,10 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, 
}



static struct intel_shared_dpll *

icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,

icl_get_dpll(struct intel_crtc_state *crtc_state,

	     struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

	struct intel_digital_port *intel_dig_port;

	struct intel_shared_dpll *pll;

	struct intel_dpll_hw_state pll_state = {};
@@ -3377,31 +3377,29 @@ void intel_shared_dpll_init(struct drm_device *dev) 


/**

 * intel_get_shared_dpll - get a shared DPLL for CRTC and encoder combination

 * @crtc: CRTC

 * @crtc_state: atomic state for @crtc

 * @crtc_state: atomic state for the crtc

 * @encoder: encoder

 *

 * Find an appropriate DPLL for the given CRTC and encoder combination. A

 * reference from the @crtc to the returned pll is registered in the atomic

 * state. That configuration is made effective by calling

 * reference from the @crtc_state to the returned pll is registered in the

 * atomic state. That configuration is made effective by calling

 * intel_shared_dpll_swap_state(). The reference should be released by calling

 * intel_release_shared_dpll().

 *

 * Returns:

 * A shared DPLL to be used by @crtc and @encoder with the given @crtc_state.

 * A shared DPLL to be used by @crtc_state and @encoder.

 */

struct intel_shared_dpll *

intel_get_shared_dpll(struct intel_crtc *crtc,

		      struct intel_crtc_state *crtc_state,

intel_get_shared_dpll(struct intel_crtc_state *crtc_state,

		      struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;



	if (WARN_ON(!dpll_mgr))

		return NULL;



	return dpll_mgr->get_dpll(crtc, crtc_state, encoder);

	return dpll_mgr->get_dpll(crtc_state, encoder);

}



/**

drivers/gpu/drm/i915/intel_dpll_mgr.h

+1 −2
Original line number Diff line number Diff line
@@ -327,8 +327,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv, 
			bool state);

#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)

#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)

struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,

						struct intel_crtc_state *state,

struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc_state *state,

						struct intel_encoder *encoder);

void intel_release_shared_dpll(struct intel_shared_dpll *dpll,

			       struct intel_crtc *crtc,

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