Commit cc022ebc authored by Andreas Färber's avatar Andreas Färber
Browse files

arm64: dts: realtek: rtd16xx: Introduce iso and misc syscon 



Group UART0 into an Isolation syscon mfd node.
Group UART1 and UART2 into a Miscellaneous syscon mfd node.

Acked-by: default avatarJames Tai <james.tai@realtek.com>
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent a5360a35

arch/arm64/boot/dts/realtek/rtd16xx.dtsi

+46 −24
Original line number Diff line number Diff line
@@ -137,19 +137,52 @@ 
			#size-cells = <1>;

			ranges = <0x0 0x98000000 0x200000>;



			uart0: serial0@7800 {

			iso: syscon@7000 {

				compatible = "syscon", "simple-mfd";

				reg = <0x7000 0x1000>;

				reg-io-width = <4>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0x0 0x7000 0x1000>;

			};



			misc: syscon@1b000 {

				compatible = "syscon", "simple-mfd";

				reg = <0x1b000 0x1000>;

				reg-io-width = <4>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0x0 0x1b000 0x1000>;

			};

		};



		gic: interrupt-controller@ff100000 {

			compatible = "arm,gic-v3";

			reg = <0xff100000 0x10000>,

			      <0xff140000 0xc0000>;

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <3>;

		};

	};

};



&iso {

	uart0: serial0@800 {

		compatible = "snps,dw-apb-uart";

				reg = <0x7800 0x400>;

		reg = <0x800 0x400>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

		clock-frequency = <27000000>;

		status = "disabled";

	};

};



			uart1: serial1@1b200 {

&misc {

	uart1: serial1@200 {

		compatible = "snps,dw-apb-uart";

				reg = <0x1b200 0x400>;

		reg = <0x200 0x400>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
@@ -157,9 +190,9 @@ 
		status = "disabled";

	};



			uart2: serial2@1b400 {

	uart2: serial2@400 {

		compatible = "snps,dw-apb-uart";

				reg = <0x1b400 0x400>;

		reg = <0x400 0x400>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
@@ -167,14 +200,3 @@ 
		status = "disabled";

	};

};
 


		gic: interrupt-controller@ff100000 {

			compatible = "arm,gic-v3";

			reg = <0xff100000 0x10000>,

			      <0xff140000 0xc0000>;

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <3>;

		};

	};

};

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