Commit cbfa447e authored by Yazen Ghannam's avatar Yazen Ghannam Committed by Borislav Petkov
Browse files

x86/MCE/AMD, EDAC/mce_amd: Add new MP5, NBIO, and PCIE SMCA bank types 



Add the (HWID, MCATYPE) tuples and names for the new MP5, NBIO, and
PCIE SMCA bank types.

Also, add their respective error descriptions to the MCE decoding module
edac_mce_amd.

Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Pu Wen <puwen@hygon.cn>
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: Shirish S <Shirish.S@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20190201225534.8177-2-Yazen.Ghannam@amd.com
parent 6e1849ec

arch/x86/include/asm/mce.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -312,6 +312,9 @@ enum smca_bank_types { 
	SMCA_PB,	/* Parameter Block */

	SMCA_PB,	/* Parameter Block */

	SMCA_PSP,	/* Platform Security Processor */

	SMCA_PSP,	/* Platform Security Processor */

	SMCA_SMU,	/* System Management Unit */

	SMCA_SMU,	/* System Management Unit */

	SMCA_MP5,	/* Microprocessor 5 Unit */

	SMCA_NBIO,	/* Northbridge IO Unit */

	SMCA_PCIE,	/* PCI Express Unit */

	N_SMCA_BANK_TYPES

	N_SMCA_BANK_TYPES

};

};

arch/x86/kernel/cpu/mce/amd.c

+12 −0
Original line number Original line Diff line number Diff line
@@ -93,6 +93,9 @@ static struct smca_bank_name smca_names[] = { 
	[SMCA_PB]	= { "param_block",	"Parameter Block" },

	[SMCA_PB]	= { "param_block",	"Parameter Block" },

	[SMCA_PSP]	= { "psp",		"Platform Security Processor" },

	[SMCA_PSP]	= { "psp",		"Platform Security Processor" },

	[SMCA_SMU]	= { "smu",		"System Management Unit" },

	[SMCA_SMU]	= { "smu",		"System Management Unit" },

	[SMCA_MP5]	= { "mp5",		"Microprocessor 5 Unit" },

	[SMCA_NBIO]	= { "nbio",		"Northbridge IO Unit" },

	[SMCA_PCIE]	= { "pcie",		"PCI Express Unit" },

};

};





static u32 smca_bank_addrs[MAX_NR_BANKS][NR_BLOCKS] __ro_after_init =

static u32 smca_bank_addrs[MAX_NR_BANKS][NR_BLOCKS] __ro_after_init =
@@ -162,6 +165,15 @@ static struct smca_hwid smca_hwid_mcatypes[] = { 




	/* System Management Unit MCA type */

	/* System Management Unit MCA type */

	{ SMCA_SMU,	 HWID_MCATYPE(0x01, 0x0), 0x1 },

	{ SMCA_SMU,	 HWID_MCATYPE(0x01, 0x0), 0x1 },



	/* Microprocessor 5 Unit MCA type */

	{ SMCA_MP5,	 HWID_MCATYPE(0x01, 0x2), 0x3FF },



	/* Northbridge IO Unit MCA type */

	{ SMCA_NBIO,	 HWID_MCATYPE(0x18, 0x0), 0x1F },



	/* PCI Express Unit MCA type */

	{ SMCA_PCIE,	 HWID_MCATYPE(0x46, 0x0), 0x1F },

};

};





struct smca_bank smca_banks[MAX_NR_BANKS];

struct smca_bank smca_banks[MAX_NR_BANKS];

drivers/edac/mce_amd.c

+32 −0
Original line number Original line Diff line number Diff line
@@ -285,6 +285,35 @@ static const char * const smca_smu_mce_desc[] = { 
	"SMU RAM ECC or parity error",

	"SMU RAM ECC or parity error",

};

};





static const char * const smca_mp5_mce_desc[] = {

	"High SRAM ECC or parity error",

	"Low SRAM ECC or parity error",

	"Data Cache Bank A ECC or parity error",

	"Data Cache Bank B ECC or parity error",

	"Data Tag Cache Bank A ECC or parity error",

	"Data Tag Cache Bank B ECC or parity error",

	"Instruction Cache Bank A ECC or parity error",

	"Instruction Cache Bank B ECC or parity error",

	"Instruction Tag Cache Bank A ECC or parity error",

	"Instruction Tag Cache Bank B ECC or parity error",

};



static const char * const smca_nbio_mce_desc[] = {

	"ECC or Parity error",

	"PCIE error",

	"SDP ErrEvent error",

	"SDP Egress Poison Error",

	"IOHC Internal Poison Error",

};



static const char * const smca_pcie_mce_desc[] = {

	"CCIX PER Message logging",

	"CCIX Read Response with Status: Non-Data Error",

	"CCIX Write Response with Status: Non-Data Error",

	"CCIX Read Response with Status: Data Error",

	"CCIX Non-okay write response with data error",

};



struct smca_mce_desc {

struct smca_mce_desc {

	const char * const *descs;

	const char * const *descs;

	unsigned int num_descs;

	unsigned int num_descs;
@@ -304,6 +333,9 @@ static struct smca_mce_desc smca_mce_descs[] = { 
	[SMCA_PB]	= { smca_pb_mce_desc,	ARRAY_SIZE(smca_pb_mce_desc)	},

	[SMCA_PB]	= { smca_pb_mce_desc,	ARRAY_SIZE(smca_pb_mce_desc)	},

	[SMCA_PSP]	= { smca_psp_mce_desc,	ARRAY_SIZE(smca_psp_mce_desc)	},

	[SMCA_PSP]	= { smca_psp_mce_desc,	ARRAY_SIZE(smca_psp_mce_desc)	},

	[SMCA_SMU]	= { smca_smu_mce_desc,	ARRAY_SIZE(smca_smu_mce_desc)	},

	[SMCA_SMU]	= { smca_smu_mce_desc,	ARRAY_SIZE(smca_smu_mce_desc)	},

	[SMCA_MP5]	= { smca_mp5_mce_desc,	ARRAY_SIZE(smca_mp5_mce_desc)	},

	[SMCA_NBIO]	= { smca_nbio_mce_desc,	ARRAY_SIZE(smca_nbio_mce_desc)	},

	[SMCA_PCIE]	= { smca_pcie_mce_desc,	ARRAY_SIZE(smca_pcie_mce_desc)	},

};

};





static bool f12h_mc0_mce(u16 ec, u8 xec)

static bool f12h_mc0_mce(u16 ec, u8 xec)

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