Commit cbf4f732 authored by Vitor Soares's avatar Vitor Soares Committed by Boris Brezillon
Browse files

i3c: add mixed limited bus mode 



The i3c bus spec defines a bus configuration where i2c devices don't
have a 50ns filter but support SCL running at SDR max rate (12.5MHz).

This patch introduces the limited bus mode so that users can use
a higher speed in presence of i2c devices index 1.

Signed-off-by: default avatarVitor Soares <vitor.soares@synopsys.com>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Cc: <linux-kernel@vger.kernel.org>
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
parent ecc8fb54

drivers/i3c/master.c

+5 −0
Original line number Diff line number Diff line
@@ -470,6 +470,7 @@ static int i3c_bus_init(struct i3c_bus *i3cbus) 
static const char * const i3c_bus_mode_strings[] = {

	[I3C_BUS_MODE_PURE] = "pure",

	[I3C_BUS_MODE_MIXED_FAST] = "mixed-fast",

	[I3C_BUS_MODE_MIXED_LIMITED] = "mixed-limited",

	[I3C_BUS_MODE_MIXED_SLOW] = "mixed-slow",

};
@@ -584,6 +585,7 @@ int i3c_bus_set_mode(struct i3c_bus *i3cbus, enum i3c_bus_mode mode, 
			i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;

		break;

	case I3C_BUS_MODE_MIXED_FAST:

	case I3C_BUS_MODE_MIXED_LIMITED:

		if (!i3cbus->scl_rate.i3c)

			i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;

		if (!i3cbus->scl_rate.i2c)
@@ -2487,6 +2489,9 @@ int i3c_master_register(struct i3c_master_controller *master, 
				mode = I3C_BUS_MODE_MIXED_FAST;

			break;

		case I3C_LVR_I2C_INDEX(1):

			if (mode < I3C_BUS_MODE_MIXED_LIMITED)

				mode = I3C_BUS_MODE_MIXED_LIMITED;

			break;

		case I3C_LVR_I2C_INDEX(2):

			if (mode < I3C_BUS_MODE_MIXED_SLOW)

				mode = I3C_BUS_MODE_MIXED_SLOW;

include/linux/i3c/master.h

+5 −0
Original line number Diff line number Diff line
@@ -250,12 +250,17 @@ struct i3c_device { 
 *			     the bus. The only impact in this mode is that the

 *			     high SCL pulse has to stay below 50ns to trick I2C

 *			     devices when transmitting I3C frames

 * @I3C_BUS_MODE_MIXED_LIMITED: I2C devices without 50ns spike filter are

 *				present on the bus. However they allow

 *				compliance up to the maximum SDR SCL clock

 *				frequency.

 * @I3C_BUS_MODE_MIXED_SLOW: I2C devices without 50ns spike filter are present

 *			     on the bus

 */

enum i3c_bus_mode {

	I3C_BUS_MODE_PURE,

	I3C_BUS_MODE_MIXED_FAST,

	I3C_BUS_MODE_MIXED_LIMITED,

	I3C_BUS_MODE_MIXED_SLOW,

};

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