Commit cbf2829b authored by Bryan O'Donoghue's avatar Bryan O'Donoghue Committed by H. Peter Anvin
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x86, apic: APIC code touches invalid MSR on P5 class machines 



Current APIC code assumes MSR_IA32_APICBASE is present for all systems.
Pentium Classic P5 and friends didn't have this MSR. MSR_IA32_APICBASE
was introduced as an architectural MSR by Intel @ P6.

Code paths that can touch this MSR invalidly are when vendor == Intel &&
cpu-family == 5 and APIC bit is set in CPUID - or when you simply pass
lapic on the kernel command line, on a P5.

The below patch stops Linux incorrectly interfering with the
MSR_IA32_APICBASE for P5 class machines. Other code paths exist that
touch the MSR - however those paths are not currently reachable for a
conformant P5.

Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linux.intel.com>
Link: http://lkml.kernel.org/r/4F8EEDD3.1080404@linux.intel.com


Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
Cc: <stable@vger.kernel.org>
parent 089f9fba

arch/x86/kernel/apic/apic.c

+20 −14
Original line number Original line Diff line number Diff line
@@ -1637,9 +1637,11 @@ static int __init apic_verify(void) 
	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;

	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;





	/* The BIOS may have set up the APIC at some other address */

	/* The BIOS may have set up the APIC at some other address */

	if (boot_cpu_data.x86 >= 6) {

		rdmsr(MSR_IA32_APICBASE, l, h);

		rdmsr(MSR_IA32_APICBASE, l, h);

		if (l & MSR_IA32_APICBASE_ENABLE)

		if (l & MSR_IA32_APICBASE_ENABLE)

			mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;

			mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;

	}





	pr_info("Found and enabled local APIC!\n");

	pr_info("Found and enabled local APIC!\n");

	return 0;

	return 0;
@@ -1657,6 +1659,7 @@ int __init apic_force_enable(unsigned long addr) 
	 * MSR. This can only be done in software for Intel P6 or later

	 * MSR. This can only be done in software for Intel P6 or later

	 * and AMD K7 (Model > 1) or later.

	 * and AMD K7 (Model > 1) or later.

	 */

	 */

	if (boot_cpu_data.x86 >= 6) {

		rdmsr(MSR_IA32_APICBASE, l, h);

		rdmsr(MSR_IA32_APICBASE, l, h);

		if (!(l & MSR_IA32_APICBASE_ENABLE)) {

		if (!(l & MSR_IA32_APICBASE_ENABLE)) {

			pr_info("Local APIC disabled by BIOS -- reenabling.\n");

			pr_info("Local APIC disabled by BIOS -- reenabling.\n");
@@ -1665,6 +1668,7 @@ int __init apic_force_enable(unsigned long addr) 
			wrmsr(MSR_IA32_APICBASE, l, h);

			wrmsr(MSR_IA32_APICBASE, l, h);

			enabled_via_apicbase = 1;

			enabled_via_apicbase = 1;

		}

		}

	}

	return apic_verify();

	return apic_verify();

}

}
@@ -2209,11 +2213,13 @@ static void lapic_resume(void) 
		 * FIXME! This will be wrong if we ever support suspend on

		 * FIXME! This will be wrong if we ever support suspend on

		 * SMP! We'll need to do this as part of the CPU restore!

		 * SMP! We'll need to do this as part of the CPU restore!

		 */

		 */

		if (boot_cpu_data.x86 >= 6) {

			rdmsr(MSR_IA32_APICBASE, l, h);

			rdmsr(MSR_IA32_APICBASE, l, h);

			l &= ~MSR_IA32_APICBASE_BASE;

			l &= ~MSR_IA32_APICBASE_BASE;

			l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;

			l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;

			wrmsr(MSR_IA32_APICBASE, l, h);

			wrmsr(MSR_IA32_APICBASE, l, h);

		}

		}

	}





	maxlvt = lapic_get_maxlvt();

	maxlvt = lapic_get_maxlvt();

	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);

	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);

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