Merge tag 'ux500-cleanup-v4.2' of... (cbdf76ab) · Commits · 戴 / test

arch/arm/mach-ux500/cache-l2x0.c

+10 −1

Original line number	Diff line number	Diff line
		@@ -6,6 +6,7 @@

		#include <linux/io.h>
		#include <linux/of.h>
		#include <linux/of_address.h>

		#include <asm/hardware/cache-l2x0.h>

		@@ -15,7 +16,14 @@
		static int __init ux500_l2x0_unlock(void)
		{
		int i;
		void __iomem *l2x0_base = __io_address(U8500_L2CC_BASE);
		struct device_node *np;
		void __iomem *l2x0_base;

		np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
		l2x0_base = of_iomap(np, 0);
		of_node_put(np);
		if (!l2x0_base)
		return -ENODEV;

		/*
		* Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
		@@ -30,6 +38,7 @@ static int __init ux500_l2x0_unlock(void)
		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
		i * L2X0_LOCKDOWN_STRIDE);
		}
		iounmap(l2x0_base);
		return 0;
		}

arch/arm/mach-ux500/cpu-db8500.c

+7 −42

Original line number	Diff line number	Diff line
		@@ -43,49 +43,10 @@ static struct prcmu_pdata db8500_prcmu_pdata = {
		.legacy_offset = DB8500_PRCMU_LEGACY_OFFSET,
		};

		/* minimum static i/o mapping required to boot U8500 platforms */
		static struct map_desc u8500_uart_io_desc[] __initdata = {
		__IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
		__IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
		};

		/* U8500 and U9540 common io_desc */
		static struct map_desc u8500_common_io_desc[] __initdata = {
		/* SCU base also covers GIC CPU BASE and TWD with its 4K page */
		__IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
		__IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
		__IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
		__IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
		};

		/* U8500 IO map specific description */
		static struct map_desc u8500_io_desc[] __initdata = {
		__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
		__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),

		};

		/* U9540 IO map specific description */
		static struct map_desc u9540_io_desc[] __initdata = {
		__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K),
		__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K),
		};

		static void __init u8500_map_io(void)
		{
		/*
		* Map the UARTs early so that the DEBUG_LL stuff continues to work.
		*/
		iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));

		ux500_map_io();

		iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));

		if (cpu_is_ux540_family())
		iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
		else
		iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
		debug_ll_io_init();
		ux500_setup_id();
		}

		/*
		@@ -114,14 +75,18 @@ static struct arm_pmu_platdata db8500_pmu_platdata = {

		static const char *db8500_read_soc_id(void)
		{
		void __iomem *uid = __io_address(U8500_BB_UID_BASE);
		void __iomem *uid;

		uid = ioremap(U8500_BB_UID_BASE, 0x20);
		if (!uid)
		return NULL;
		/* Throw these device-specific numbers into the entropy pool */
		add_device_randomness(uid, 0x14);
		return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
		readl((u32 *)uid+0),
		readl((u32 )uid+1), readl((u32 )uid+2),
		readl((u32 )uid+3), readl((u32 )uid+4));
		iounmap(uid);
		}

		static struct device * __init db8500_soc_device_init(void)

arch/arm/mach-ux500/cpu.c

+13 −7

Original line number	Diff line number	Diff line
		@@ -16,6 +16,7 @@
		#include <linux/stat.h>
		#include <linux/of.h>
		#include <linux/of_irq.h>
		#include <linux/of_address.h>
		#include <linux/irq.h>
		#include <linux/irqchip.h>
		#include <linux/irqchip/arm-gic.h>
		@@ -52,31 +53,36 @@ void ux500_restart(enum reboot_mode mode, const char *cmd)
		*/
		void __init ux500_init_irq(void)
		{
		struct device_node *np;
		struct resource r;

		gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND);
		irqchip_init();
		np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
		of_address_to_resource(np, 0, &r);
		of_node_put(np);
		if (!r.start) {
		pr_err("could not find PRCMU base resource\n");
		return;
		}
		prcmu_early_init(r.start, r.end-r.start);
		ux500_pm_init(r.start, r.end-r.start);

		/*
		* Init clocks here so that they are available for system timer
		* initialization.
		*/
		if (cpu_is_u8500_family()) {
		prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
		ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);

		u8500_of_clk_init(U8500_CLKRST1_BASE,
		U8500_CLKRST2_BASE,
		U8500_CLKRST3_BASE,
		U8500_CLKRST5_BASE,
		U8500_CLKRST6_BASE);
		} else if (cpu_is_u9540()) {
		prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
		ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
		u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
		U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
		U8500_CLKRST6_BASE);
		} else if (cpu_is_u8540()) {
		prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
		ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
		u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
		U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
		U8500_CLKRST6_BASE);

arch/arm/mach-ux500/id.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -72,7 +72,7 @@ static unsigned int partnumber(unsigned int asicid)
		* DB9540 0x413fc090 0xFFFFDBF4 0x009540xx
		*/

		void __init ux500_map_io(void)
		void __init ux500_setup_id(void)
		{
		unsigned int cpuid = read_cpuid_id();
		unsigned int asicid = 0;

arch/arm/mach-ux500/platsmp.c

+14 −21

Original line number	Diff line number	Diff line
		@@ -16,6 +16,8 @@
		#include <linux/device.h>
		#include <linux/smp.h>
		#include <linux/io.h>
		#include <linux/of.h>
		#include <linux/of_address.h>

		#include <asm/cacheflush.h>
		#include <asm/smp_plat.h>
		@@ -26,6 +28,9 @@
		#include "db8500-regs.h"
		#include "id.h"

		static void __iomem *scu_base;
		static void __iomem *backupram;

		/* This is called from headsmp.S to wakeup the secondary core */
		extern void u8500_secondary_startup(void);

		@@ -41,16 +46,6 @@ static void write_pen_release(int val)
		sync_cache_w(&pen_release);
		}

		static void __iomem *scu_base_addr(void)
		{
		if (cpu_is_u8500_family() \|\| cpu_is_ux540_family())
		return __io_address(U8500_SCU_BASE);
		else
		ux500_unknown_soc();

		return NULL;
		}

		static DEFINE_SPINLOCK(boot_lock);

		static void ux500_secondary_init(unsigned int cpu)
		@@ -104,13 +99,6 @@ static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)

		static void __init wakeup_secondary(void)
		{
		void __iomem *backupram;

		if (cpu_is_u8500_family() \|\| cpu_is_ux540_family())
		backupram = __io_address(U8500_BACKUPRAM0_BASE);
		else
		ux500_unknown_soc();

		/*
		* write the address of secondary startup into the backup ram register
		* at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
		@@ -135,10 +123,16 @@ static void __init wakeup_secondary(void)
		*/
		static void __init ux500_smp_init_cpus(void)
		{
		void __iomem *scu_base = scu_base_addr();
		unsigned int i, ncores;
		struct device_node *np;

		ncores = scu_base ? scu_get_core_count(scu_base) : 1;
		np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
		scu_base = of_iomap(np, 0);
		of_node_put(np);
		if (!scu_base)
		return;
		backupram = ioremap(U8500_BACKUPRAM0_BASE, SZ_8K);
		ncores = scu_get_core_count(scu_base);

		/* sanity check */
		if (ncores > nr_cpu_ids) {
		@@ -153,8 +147,7 @@ static void __init ux500_smp_init_cpus(void)

		static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
		{

		scu_enable(scu_base_addr());
		scu_enable(scu_base);
		wakeup_secondary();
		}

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