Merge tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

  regions, used when the GIC doesn't have banked registers. The offset is

  cpu-offset * cpu-nr.

- arm,routable-irqs : Total number of gic irq inputs which are not directly

		  connected from the peripherals, but are routed dynamically

		  by a crossbar/multiplexer preceding the GIC. The GIC irq

		  input line is assigned dynamically when the corresponding

		  peripheral's crossbar line is mapped.

Example:

	intc: interrupt-controller@fff11000 {

		#interrupt-cells = <3>;

		#address-cells = <1>;

		interrupt-controller;

		arm,routable-irqs = <160>;

		reg = <0xfff11000 0x1000>,

		      <0xfff10100 0x100>;

	};

Some socs have a large number of interrupts requests to service

the needs of its many peripherals and subsystems. All of the

interrupt lines from the subsystems are not needed at the same

time, so they have to be muxed to the irq-controller appropriately.

In such places a interrupt controllers are preceded by an CROSSBAR

that provides flexibility in muxing the device requests to the controller

inputs.

Required properties:

- compatible : Should be "ti,irq-crossbar"

- reg: Base address and the size of the crossbar registers.

- ti,max-irqs: Total number of irqs available at the interrupt controller.

- ti,reg-size: Size of a individual register in bytes. Every individual

	    register is assumed to be of same size. Valid sizes are 1, 2, 4.

- ti,irqs-reserved: List of the reserved irq lines that are not muxed using

		 crossbar. These interrupt lines are reserved in the soc,

		 so crossbar bar driver should not consider them as free

		 lines.

Examples:

		crossbar_mpu: @4a020000 {

			compatible = "ti,irq-crossbar";

			reg = <0x4a002a48 0x130>;

			ti,max-irqs = <160>;

			ti,reg-size = <2>;

			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;

		};

Clock bindings for ARM Integrator Core Module clocks

Auxilary Oscillator Clock

This is a configurable clock fed from a 24 MHz chrystal,

used for generating e.g. video clocks. It is located on the

core module and there is only one of these.

This clock node *must* be a subnode of the core module, since

it obtains the base address for it's address range from its

parent node.

Required properties:

- compatible: must be "arm,integrator-cm-auxosc"

- #clock-cells: must be <0>

Optional properties:

- clocks: parent clock(s)

Example:

core-module@10000000 {

	xtal24mhz: xtal24mhz@24M {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

	};

	auxosc: cm_aux_osc@25M {

		#clock-cells = <0>;

		compatible = "arm,integrator-cm-auxosc";

		clocks = <&xtal24mhz>;

	};

};

* Altera SOCFPGA specific extensions to the Synopsys Designware Mobile

  Storage Host Controller

The Synopsys designware mobile storage host controller is used to interface

a SoC with storage medium such as eMMC or SD/MMC cards. This file documents

differences between the core Synopsys dw mshc controller properties described

by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific

extensions to the Synopsys Designware Mobile Storage Host Controller.

Required Properties:

* compatible: should be

	- "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform

Example:

	mmc: dwmmc0@ff704000 {

		compatible = "altr,socfpga-dw-mshc";

		reg = <0xff704000 0x1000>;

		interrupts = <0 129 4>;

		#address-cells = <1>;

		#size-cells = <0>;

	};

microcontroller to turn the power off. This driver adds a handler to

pm_power_off which is called to turn the power off.

Synology NAS devices use a similar scheme, but a different baud rate,

9600, and a different character, '1'.

Required Properties:

- compatible: Should be "qnap,power-off"

- compatible: Should be "qnap,power-off" or "synology,power-off"

- reg: Address and length of the register set for UART1

- clocks: tclk clock