Commit cbb51afa authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev 

* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: (24 commits)
  pci: allow multiple calls to pcim_enable_device()
  Blackfin pata-bf54x driver: fix compiling bug - no ata_port struct in struct ata_device any more
  Blackfin pata-bf54x driver: should cover all possible interrupt sources
  Blackfin pata-bf54x driver: Add debug information
  Blackfin pata-bf54x driver: Remove obsolete PM function
  pata_sl82c105: dual channel support
  ata_piix.c: make piix_merge_scr() static
  sata_nv: fix for completion handling
  sata_mv: Remove PCI dependency
  sata_mv ncq Comments and version bump
  sata_mv ncq Remove post internal cmd op
  sata_mv ncq Enable NCQ operation
  sata_mv ncq Introduce per-tag SG tables
  ata_piix: IDE mode SATA patch for Intel ICH10 DeviceID's
  ahci: RAID mode SATA patch for Intel ICH10 DeviceID's
  sata_mv ncq Use DMA memory pools for hardware memory tables
  sata_mv ncq Restrict max sectors to 8-bits on GenII NCQ
  sata_mv ncq Ignore response status LSB on NCQ
  sata_mv ncq Use hqtag instead of ioid
  sata_mv ncq Add want ncq parameter for EDMA configuration
  ...
parents dd5f5fed b95d58ea

drivers/ata/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ config ATA_PIIX 


config SATA_MV

	tristate "Marvell SATA support (HIGHLY EXPERIMENTAL)"

	depends on PCI && EXPERIMENTAL

	depends on EXPERIMENTAL

	help

	  This option enables support for the Marvell Serial ATA family.

	  Currently supports 88SX[56]0[48][01] chips.

drivers/ata/ahci.c

+2 −0
Original line number Diff line number Diff line
@@ -475,6 +475,8 @@ static const struct pci_device_id ahci_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */

	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */

	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */

	{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */



	/* JMicron 360/1/3/5/6, match class to avoid IDE function */

	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,

drivers/ata/ata_piix.c

+9 −1
Original line number Diff line number Diff line
@@ -267,6 +267,14 @@ static const struct pci_device_id piix_pci_tbl[] = { 
	{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },

	/* SATA Controller IDE (Tolapai) */

	{ 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },

	/* SATA Controller IDE (ICH10) */

	{ 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },

	/* SATA Controller IDE (ICH10) */

	{ 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },

	/* SATA Controller IDE (ICH10) */

	{ 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },

	/* SATA Controller IDE (ICH10) */

	{ 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },



	{ }	/* terminate list */

};
@@ -1068,7 +1076,7 @@ static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val) 
	iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);

}



u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)

static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)

{

	u32 val = 0;

	int i, mi;

drivers/ata/pata_bf54x.c

+24 −29
Original line number Diff line number Diff line
@@ -299,7 +299,7 @@ static void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev) 
	*/

	n6 = num_clocks_min(t6min, fsclk);

	if (mode >= 0 && mode <= 4 && n6 >= 1) {

		pr_debug("set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);

		dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);

		/* calculate the timing values for register transfers. */

		while (mode > 0 && pio_fsclk[mode] > fsclk)

			mode--;
@@ -376,7 +376,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev) 


	mode = adev->dma_mode - XFER_UDMA_0;

	if (mode >= 0 && mode <= 5) {

		pr_debug("set udmamode: mode=%d\n", mode);

		dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode);

		/* the most restrictive timing value is t6 and tc,

		 * the DIOW - data hold. If one SCLK pulse is longer

		 * than this minimum value then register
@@ -433,7 +433,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev) 


	mode = adev->dma_mode - XFER_MW_DMA_0;

	if (mode >= 0 && mode <= 2) {

		pr_debug("set mdmamode: mode=%d\n", mode);

		dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode);

		/* the most restrictive timing value is tf, the DMACK to

		 * read data released. If one SCLK pulse is longer than

		 * this maximum value then the MDMA mode
@@ -697,7 +697,7 @@ static void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 
			write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal);

			write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam);

			write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah);

			pr_debug("hob: feat 0x%X nsect 0x%X, lba 0x%X "

			dev_dbg(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X "

				 "0x%X 0x%X\n",

				tf->hob_feature,

				tf->hob_nsect,
@@ -711,7 +711,7 @@ static void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 
		write_atapi_register(base, ATA_REG_LBAL, tf->lbal);

		write_atapi_register(base, ATA_REG_LBAM, tf->lbam);

		write_atapi_register(base, ATA_REG_LBAH, tf->lbah);

		pr_debug("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",

		dev_dbg(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",

			tf->feature,

			tf->nsect,

			tf->lbal,
@@ -721,7 +721,7 @@ static void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 


	if (tf->flags & ATA_TFLAG_DEVICE) {

		write_atapi_register(base, ATA_REG_DEVICE, tf->device);

		pr_debug("device 0x%X\n", tf->device);

		dev_dbg(ap->dev, "device 0x%X\n", tf->device);

	}



	ata_wait_idle(ap);
@@ -782,7 +782,7 @@ static void bfin_exec_command(struct ata_port *ap, 
			      const struct ata_taskfile *tf)

{

	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;

	pr_debug("ata%u: cmd 0x%X\n", ap->print_id, tf->command);

	dev_dbg(ap->dev, "ata%u: cmd 0x%X\n", ap->print_id, tf->command);



	write_atapi_register(base, ATA_REG_CMD, tf->command);

	ata_pause(ap);
@@ -834,7 +834,7 @@ static void bfin_bmdma_setup(struct ata_queued_cmd *qc) 
	struct scatterlist *sg;

	unsigned int si;



	pr_debug("in atapi dma setup\n");

	dev_dbg(qc->ap->dev, "in atapi dma setup\n");

	/* Program the ATA_CTRL register with dir */

	if (qc->tf.flags & ATA_TFLAG_WRITE) {

		/* fill the ATAPI DMA controller */
@@ -870,7 +870,7 @@ static void bfin_bmdma_start(struct ata_queued_cmd *qc) 
	struct scatterlist *sg;

	unsigned int si;



	pr_debug("in atapi dma start\n");

	dev_dbg(qc->ap->dev, "in atapi dma start\n");

	if (!(ap->udma_mask || ap->mwdma_mask))

		return;
@@ -888,7 +888,7 @@ static void bfin_bmdma_start(struct ata_queued_cmd *qc) 
				sg_dma_address(sg) + sg_dma_len(sg));

		}

		enable_dma(CH_ATAPI_TX);

		pr_debug("enable udma write\n");

		dev_dbg(qc->ap->dev, "enable udma write\n");



		/* Send ATA DMA write command */

		bfin_exec_command(ap, &qc->tf);
@@ -898,7 +898,7 @@ static void bfin_bmdma_start(struct ata_queued_cmd *qc) 
			| XFER_DIR));

	} else {

		enable_dma(CH_ATAPI_RX);

		pr_debug("enable udma read\n");

		dev_dbg(qc->ap->dev, "enable udma read\n");



		/* Send ATA DMA read command */

		bfin_exec_command(ap, &qc->tf);
@@ -936,7 +936,7 @@ static void bfin_bmdma_stop(struct ata_queued_cmd *qc) 
	struct scatterlist *sg;

	unsigned int si;



	pr_debug("in atapi dma stop\n");

	dev_dbg(qc->ap->dev, "in atapi dma stop\n");

	if (!(ap->udma_mask || ap->mwdma_mask))

		return;
@@ -1147,15 +1147,15 @@ static unsigned char bfin_bmdma_status(struct ata_port *ap) 
	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;

	unsigned short int_status = ATAPI_GET_INT_STATUS(base);



	if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON|ULTRA_XFER_ON)) {

	if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON|ULTRA_XFER_ON))

		host_stat |= ATA_DMA_ACTIVE;

	}

	if (int_status & (MULTI_DONE_INT|UDMAIN_DONE_INT|UDMAOUT_DONE_INT)) {

	if (int_status & (MULTI_DONE_INT|UDMAIN_DONE_INT|UDMAOUT_DONE_INT|

		ATAPI_DEV_INT))

		host_stat |= ATA_DMA_INTR;

	}

	if (int_status & (MULTI_TERM_INT|UDMAIN_TERM_INT|UDMAOUT_TERM_INT)) {

		host_stat |= ATA_DMA_ERR;

	}

	if (int_status & (MULTI_TERM_INT|UDMAIN_TERM_INT|UDMAOUT_TERM_INT))

		host_stat |= ATA_DMA_ERR|ATA_DMA_INTR;



	dev_dbg(ap->dev, "ATAPI: host_stat=0x%x\n", host_stat);



	return host_stat;

}
@@ -1213,8 +1213,7 @@ static void bfin_irq_clear(struct ata_port *ap) 
{

	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;



	pr_debug("in atapi irq clear\n");



	dev_dbg(ap->dev, "in atapi irq clear\n");

	ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT

		| MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT

		| MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
@@ -1232,7 +1231,7 @@ static unsigned char bfin_irq_on(struct ata_port *ap) 
	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;

	u8 tmp;



	pr_debug("in atapi irq on\n");

	dev_dbg(ap->dev, "in atapi irq on\n");

	ap->ctl &= ~ATA_NIEN;

	ap->last_ctl = ap->ctl;
@@ -1255,7 +1254,7 @@ static void bfin_bmdma_freeze(struct ata_port *ap) 
{

	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;



	pr_debug("in atapi dma freeze\n");

	dev_dbg(ap->dev, "in atapi dma freeze\n");

	ap->ctl |= ATA_NIEN;

	ap->last_ctl = ap->ctl;
@@ -1328,7 +1327,7 @@ static void bfin_error_handler(struct ata_port *ap) 


static void bfin_port_stop(struct ata_port *ap)

{

	pr_debug("in atapi port stop\n");

	dev_dbg(ap->dev, "in atapi port stop\n");

	if (ap->udma_mask != 0 || ap->mwdma_mask != 0) {

		free_dma(CH_ATAPI_RX);

		free_dma(CH_ATAPI_TX);
@@ -1337,7 +1336,7 @@ static void bfin_port_stop(struct ata_port *ap) 


static int bfin_port_start(struct ata_port *ap)

{

	pr_debug("in atapi port start\n");

	dev_dbg(ap->dev, "in atapi port start\n");

	if (!(ap->udma_mask || ap->mwdma_mask))

		return 0;
@@ -1373,10 +1372,6 @@ static struct scsi_host_template bfin_sht = { 
	.slave_configure	= ata_scsi_slave_config,

	.slave_destroy		= ata_scsi_slave_destroy,

	.bios_param		= ata_std_bios_param,

#ifdef CONFIG_PM

	.resume			= ata_scsi_device_resume,

	.suspend		= ata_scsi_device_suspend,

#endif

};



static const struct ata_port_operations bfin_pata_ops = {

drivers/ata/pata_sl82c105.c

+31 −2
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ 
#include <linux/libata.h>



#define DRV_NAME "pata_sl82c105"

#define DRV_VERSION "0.3.2"

#define DRV_VERSION "0.3.3"



enum {

	/*
@@ -206,6 +206,34 @@ static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc) 
	sl82c105_set_piomode(ap, qc->dev);

}



/**

 *	sl82c105_qc_defer	-	implement serialization

 *	@qc: command

 *

 *	We must issue one command per host not per channel because

 *	of the reset bug.

 *

 *	Q: is the scsi host lock sufficient ?

 */



static int sl82c105_qc_defer(struct ata_queued_cmd *qc)

{

	struct ata_host *host = qc->ap->host;

	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];

	int rc;



	/* First apply the usual rules */	

	rc = ata_std_qc_defer(qc);

	if (rc != 0)

		return rc;



	/* Now apply serialization rules. Only allow a command if the

	   other channel state machine is idle */

	if (alt && alt->qc_active)

		return	ATA_DEFER_PORT;

	return 0;

}



static struct scsi_host_template sl82c105_sht = {

	.module			= THIS_MODULE,

	.name			= DRV_NAME,
@@ -245,6 +273,7 @@ static struct ata_port_operations sl82c105_port_ops = { 
	.bmdma_stop	= sl82c105_bmdma_stop,

	.bmdma_status 	= ata_bmdma_status,



	.qc_defer	= sl82c105_qc_defer,

	.qc_prep 	= ata_qc_prep,

	.qc_issue	= ata_qc_issue_prot,
@@ -312,7 +341,7 @@ static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id 
	};

	/* for now use only the first port */

	const struct ata_port_info *ppi[] = { &info_early,

					       &ata_dummy_port_info };

					       NULL };

	u32 val;

	int rev;

CRA Git | Maintained and supported by SUSTech CRA and CCSE