Commit cb8cc185 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Linus Walleij
Browse files

pinctrl: tigerlake: Fix register offsets for TGL-H variant 



It appears that almost traditionally the H variants have some deviations
in the register offsets in comparison to LP ones. This is the case for
Intel Tiger Lake as well. Fix register offsets for TGL-H variant.

Fixes: 653d9645 ("pinctrl: tigerlake: Add support for Tiger Lake-H")
Reported-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20200929110306.40852-1-andriy.shevchenko@linux.intel.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 3163508b

drivers/pinctrl/intel/pinctrl-tigerlake.c

+25 −17
Original line number Diff line number Diff line
@@ -16,8 +16,10 @@ 
#include "pinctrl-intel.h"



#define TGL_PAD_OWN		0x020

#define TGL_PADCFGLOCK	0x080

#define TGL_HOSTSW_OWN	0x0b0

#define TGL_LP_PADCFGLOCK	0x080

#define TGL_H_PADCFGLOCK	0x090

#define TGL_LP_HOSTSW_OWN	0x0b0

#define TGL_H_HOSTSW_OWN	0x0c0

#define TGL_GPI_IS		0x100

#define TGL_GPI_IE		0x120
@@ -29,12 +31,12 @@ 
		.gpio_base = (g),			\

	}



#define TGL_COMMUNITY(b, s, e, g)			\

#define TGL_COMMUNITY(b, s, e, pl, ho, g)		\

	{						\

		.barno = (b),				\

		.padown_offset = TGL_PAD_OWN,		\

		.padcfglock_offset = TGL_PADCFGLOCK,	\

		.hostown_offset = TGL_HOSTSW_OWN,	\

		.padcfglock_offset = (pl),		\

		.hostown_offset = (ho),			\

		.is_offset = TGL_GPI_IS,		\

		.ie_offset = TGL_GPI_IE,		\

		.pin_base = (s),			\
@@ -43,6 +45,12 @@ 
		.ngpps = ARRAY_SIZE(g),			\

	}



#define TGL_LP_COMMUNITY(b, s, e, g)			\

	TGL_COMMUNITY(b, s, e, TGL_LP_PADCFGLOCK, TGL_LP_HOSTSW_OWN, g)



#define TGL_H_COMMUNITY(b, s, e, g)			\

	TGL_COMMUNITY(b, s, e, TGL_H_PADCFGLOCK, TGL_H_HOSTSW_OWN, g)



/* Tiger Lake-LP */

static const struct pinctrl_pin_desc tgllp_pins[] = {

	/* GPP_B */
@@ -367,10 +375,10 @@ static const struct intel_padgroup tgllp_community5_gpps[] = { 
};



static const struct intel_community tgllp_communities[] = {

	TGL_COMMUNITY(0, 0, 66, tgllp_community0_gpps),

	TGL_COMMUNITY(1, 67, 170, tgllp_community1_gpps),

	TGL_COMMUNITY(2, 171, 259, tgllp_community4_gpps),

	TGL_COMMUNITY(3, 260, 276, tgllp_community5_gpps),

	TGL_LP_COMMUNITY(0, 0, 66, tgllp_community0_gpps),

	TGL_LP_COMMUNITY(1, 67, 170, tgllp_community1_gpps),

	TGL_LP_COMMUNITY(2, 171, 259, tgllp_community4_gpps),

	TGL_LP_COMMUNITY(3, 260, 276, tgllp_community5_gpps),

};



static const struct intel_pinctrl_soc_data tgllp_soc_data = {
@@ -723,11 +731,11 @@ static const struct intel_padgroup tglh_community5_gpps[] = { 
};



static const struct intel_community tglh_communities[] = {

	TGL_COMMUNITY(0, 0, 78, tglh_community0_gpps),

	TGL_COMMUNITY(1, 79, 180, tglh_community1_gpps),

	TGL_COMMUNITY(2, 181, 217, tglh_community3_gpps),

	TGL_COMMUNITY(3, 218, 266, tglh_community4_gpps),

	TGL_COMMUNITY(4, 267, 290, tglh_community5_gpps),

	TGL_H_COMMUNITY(0, 0, 78, tglh_community0_gpps),

	TGL_H_COMMUNITY(1, 79, 180, tglh_community1_gpps),

	TGL_H_COMMUNITY(2, 181, 217, tglh_community3_gpps),

	TGL_H_COMMUNITY(3, 218, 266, tglh_community4_gpps),

	TGL_H_COMMUNITY(4, 267, 290, tglh_community5_gpps),

};



static const struct intel_pinctrl_soc_data tglh_soc_data = {

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