Commit cb8348fe authored by Martin Leung's avatar Martin Leung Committed by Alex Deucher
Browse files

drm/amd/display: always apply T7/T9 delay logic 



[why]
before we exit early in edp_reciever_ready if we detect that panel
is not edp or below rev 1.2. This will skip the backlight/t7 delay panel
patch.

[how]
edit logic to ensure panel patch is applied regardless of edp rev.

Signed-off-by: default avatarMartin Leung <martin.leung@amd.com>
Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3b4a18a3

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

+29 −27
Original line number Diff line number Diff line
@@ -153,9 +153,9 @@ bool edp_receiver_ready_T9(struct dc_link *link) 
	unsigned char edpRev = 0;

	enum dc_status result = DC_OK;

	result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));

	if (edpRev < DP_EDP_12)

		return true;



     /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/

	if (result == DC_OK && edpRev >= DP_EDP_12) {

		do {

			sinkstatus = 1;

			result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
@@ -165,6 +165,7 @@ bool edp_receiver_ready_T9(struct dc_link *link) 
				break;

			udelay(100); //MAx T9

		} while (++tries < 50);

	}



	if (link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)

		udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
@@ -183,8 +184,8 @@ bool edp_receiver_ready_T7(struct dc_link *link) 
	unsigned long long time_taken_in_ns = 0;



	result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));

	if (result == DC_OK && edpRev < DP_EDP_12)

		return true;



	if (result == DC_OK && edpRev >= DP_EDP_12) {

		/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/

		enter_timestamp = dm_get_timestamp(link->ctx);

		do {
@@ -198,6 +199,7 @@ bool edp_receiver_ready_T7(struct dc_link *link) 
			finish_timestamp = dm_get_timestamp(link->ctx);

			time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, enter_timestamp);

		} while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms

	}



	if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0)

		udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 1000);

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