Commit cb7f3a3e authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-arm64-dt-for-v4.10' of... 

Merge tag 'renesas-arm64-dt-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Renesas ARM64 Based SoC DT Updates for v4.10

Enablement:
* Enable On-board eMMC
* Enable SDHI 0 & 3 with UHS
* Add SYS-DMAC controller nodes to r8a7796 SoC
* Populate EXTALR on r8a7796/salvator-x board; used by watchdog
* Add DU LVDS output endpoint on r8a7795/salvator-x board
* Add bias setting for USB1 pins on r8a7795/salvator-x board

Clean-Up:
* Remove FCP SoC-specific compatible strings

* tag 'renesas-arm64-dt-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  arm64: renesas: r8a7796: add SYS-DMAC controller nodes
  arm64: dts: r8a7795: salvator-x: add bias setting for usb1_pins
  arm64: dts: r8a7796: salvator: enable on board eMMC
  arm64: dts: r8a7795: salvator: enable on-board eMMC
  arm64: dts: r8a7796: salvator-x: enable UHS for SDHI 0 & 3
  arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3
  arm64: dts: r8a7796: add SDHI nodes
  arm64: dts: r8a7795: Remove FCP SoC-specific compatible strings
  dt-bindings: media: renesas-fcp: Remove SoC-specific compatible strings
  arm64: dts: r8a7795: salvator-x: Add DU LVDS output endpoint
  arm64: dts: r8a7796: salvator-x: Populate EXTALR
  arm64: dts: r8a7795: salvator-x: enable UHS for SDHI 0 & 3

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents cbd82259 93508520

Documentation/devicetree/bindings/media/renesas,fcp.txt

+1 −7
Original line number Diff line number Diff line
@@ -11,15 +11,9 @@ are paired with. These DT bindings currently support the FCPV and FCPF. 


 - compatible: Must be one or more of the following



   - "renesas,r8a7795-fcpv" for R8A7795 (R-Car H3) compatible 'FCP for VSP'

   - "renesas,r8a7795-fcpf" for R8A7795 (R-Car H3) compatible 'FCP for FDP'

   - "renesas,fcpv" for generic compatible 'FCP for VSP'

   - "renesas,fcpf" for generic compatible 'FCP for FDP'



   When compatible with the generic version, nodes must list the

   SoC-specific version corresponding to the platform first, followed by the

   family-specific and/or generic versions.



 - reg: the register base and size for the device registers

 - clocks: Reference to the functional clock
@@ -32,7 +26,7 @@ Device node example 
-------------------



	fcpvd1: fcp@fea2f000 {

		compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";

		compatible = "renesas,fcpv";

		reg = <0 0xfea2f000 0 0x200>;

		clocks = <&cpg CPG_MOD 602>;

		power-domains = <&sysc R8A7795_PD_A3VP>;

arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts

+81 −4
Original line number Diff line number Diff line
@@ -62,6 +62,24 @@ 
		clock-frequency = <24576000>;

	};



	reg_1p8v: regulator0 {

		compatible = "regulator-fixed";

		regulator-name = "fixed-1.8V";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;

		regulator-boot-on;

		regulator-always-on;

	};



	reg_3p3v: regulator1 {

		compatible = "regulator-fixed";

		regulator-name = "fixed-3.3V";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		regulator-boot-on;

		regulator-always-on;

	};



	vcc_sdhi0: regulator-vcc-sdhi0 {

		compatible = "regulator-fixed";
@@ -191,6 +209,10 @@ 
				remote-endpoint = <&adv7123_in>;

			};

		};

		port@3 {

			lvds_connector: endpoint {

			};

		};

	};

};
@@ -237,11 +259,37 @@ 
	sdhi0_pins: sd0 {

		groups = "sdhi0_data4", "sdhi0_ctrl";

		function = "sdhi0";

		power-source = <3300>;

	};



	sdhi0_pins_uhs: sd0_uhs {

		groups = "sdhi0_data4", "sdhi0_ctrl";

		function = "sdhi0";

		power-source = <1800>;

	};



	sdhi2_pins: sd2 {

		groups = "sdhi2_data8", "sdhi2_ctrl";

		function = "sdhi2";

		power-source = <3300>;

	};



	sdhi2_pins_uhs: sd2_uhs {

		groups = "sdhi2_data8", "sdhi2_ctrl";

		function = "sdhi2";

		power-source = <1800>;

	};



	sdhi3_pins: sd3 {

		groups = "sdhi3_data4", "sdhi3_ctrl";

		function = "sdhi3";

		power-source = <3300>;

	};



	sdhi3_pins_uhs: sd3_uhs {

		groups = "sdhi3_data4", "sdhi3_ctrl";

		function = "sdhi3";

		power-source = <1800>;

	};



	sound_pins: sound {
@@ -261,10 +309,22 @@ 
	};



	usb1_pins: usb1 {

		mux {

			groups = "usb1";

			function = "usb1";

		};



		ovc {

			pins = "GP_6_27";

			bias-pull-up;

		};



		pwen {

			pins = "GP_6_26";

			bias-pull-down;

		};

	};



	usb2_pins: usb2 {

		groups = "usb2";

		function = "usb2";
@@ -371,25 +431,42 @@ 


&sdhi0 {

	pinctrl-0 = <&sdhi0_pins>;

	pinctrl-names = "default";

	pinctrl-1 = <&sdhi0_pins_uhs>;

	pinctrl-names = "default", "state_uhs";



	vmmc-supply = <&vcc_sdhi0>;

	vqmmc-supply = <&vccq_sdhi0>;

	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;

	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;

	bus-width = <4>;

	sd-uhs-sdr50;

	status = "okay";

};



&sdhi2 {

	/* used for on-board 8bit eMMC */

	pinctrl-0 = <&sdhi2_pins>;

	pinctrl-1 = <&sdhi2_pins_uhs>;

	pinctrl-names = "default", "state_uhs";



	vmmc-supply = <&reg_3p3v>;

	vqmmc-supply = <&reg_1p8v>;

	bus-width = <8>;

	non-removable;

	status = "okay";

};



&sdhi3 {

	pinctrl-0 = <&sdhi3_pins>;

	pinctrl-names = "default";

	pinctrl-1 = <&sdhi3_pins_uhs>;

	pinctrl-names = "default", "state_uhs";



	vmmc-supply = <&vcc_sdhi3>;

	vqmmc-supply = <&vccq_sdhi3>;

	cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;

	wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;

	bus-width = <4>;

	sd-uhs-sdr50;

	status = "okay";

};

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -1306,28 +1306,28 @@ 
		};



		fcpvb1: fcp@fe92f000 {

			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";

			compatible = "renesas,fcpv";

			reg = <0 0xfe92f000 0 0x200>;

			clocks = <&cpg CPG_MOD 606>;

			power-domains = <&sysc R8A7795_PD_A3VP>;

		};



		fcpf0: fcp@fe950000 {

			compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";

			compatible = "renesas,fcpf";

			reg = <0 0xfe950000 0 0x200>;

			clocks = <&cpg CPG_MOD 615>;

			power-domains = <&sysc R8A7795_PD_A3VP>;

		};



		fcpf1: fcp@fe951000 {

			compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";

			compatible = "renesas,fcpf";

			reg = <0 0xfe951000 0 0x200>;

			clocks = <&cpg CPG_MOD 614>;

			power-domains = <&sysc R8A7795_PD_A3VP>;

		};



		fcpf2: fcp@fe952000 {

			compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";

			compatible = "renesas,fcpf";

			reg = <0 0xfe952000 0 0x200>;

			clocks = <&cpg CPG_MOD 613>;

			power-domains = <&sysc R8A7795_PD_A3VP>;
@@ -1344,7 +1344,7 @@ 
		};



		fcpvb0: fcp@fe96f000 {

			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";

			compatible = "renesas,fcpv";

			reg = <0 0xfe96f000 0 0x200>;

			clocks = <&cpg CPG_MOD 607>;

			power-domains = <&sysc R8A7795_PD_A3VP>;
@@ -1361,7 +1361,7 @@ 
		};



		fcpvi0: fcp@fe9af000 {

			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";

			compatible = "renesas,fcpv";

			reg = <0 0xfe9af000 0 0x200>;

			clocks = <&cpg CPG_MOD 611>;

			power-domains = <&sysc R8A7795_PD_A3VP>;
@@ -1378,7 +1378,7 @@ 
		};



		fcpvi1: fcp@fe9bf000 {

			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";

			compatible = "renesas,fcpv";

			reg = <0 0xfe9bf000 0 0x200>;

			clocks = <&cpg CPG_MOD 610>;

			power-domains = <&sysc R8A7795_PD_A3VP>;
@@ -1395,7 +1395,7 @@ 
		};



		fcpvi2: fcp@fe9cf000 {

			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";

			compatible = "renesas,fcpv";

			reg = <0 0xfe9cf000 0 0x200>;

			clocks = <&cpg CPG_MOD 609>;

			power-domains = <&sysc R8A7795_PD_A3VP>;
@@ -1412,7 +1412,7 @@ 
		};



		fcpvd0: fcp@fea27000 {

			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";

			compatible = "renesas,fcpv";

			reg = <0 0xfea27000 0 0x200>;

			clocks = <&cpg CPG_MOD 603>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -1429,7 +1429,7 @@ 
		};



		fcpvd1: fcp@fea2f000 {

			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";

			compatible = "renesas,fcpv";

			reg = <0 0xfea2f000 0 0x200>;

			clocks = <&cpg CPG_MOD 602>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -1446,7 +1446,7 @@ 
		};



		fcpvd2: fcp@fea37000 {

			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";

			compatible = "renesas,fcpv";

			reg = <0 0xfea37000 0 0x200>;

			clocks = <&cpg CPG_MOD 601>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -1463,7 +1463,7 @@ 
		};



		fcpvd3: fcp@fea3f000 {

			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";

			compatible = "renesas,fcpv";

			reg = <0 0xfea3f000 0 0x200>;

			clocks = <&cpg CPG_MOD 600>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts

+148 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 


/dts-v1/;

#include "r8a7796.dtsi"

#include <dt-bindings/gpio/gpio.h>



/ {

	model = "Renesas Salvator-X board based on r8a7796";
@@ -29,6 +30,72 @@ 
		/* first 128MB is reserved for secure area. */

		reg = <0x0 0x48000000 0x0 0x78000000>;

	};



	reg_1p8v: regulator0 {

		compatible = "regulator-fixed";

		regulator-name = "fixed-1.8V";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;

		regulator-boot-on;

		regulator-always-on;

	};



	reg_3p3v: regulator1 {

		compatible = "regulator-fixed";

		regulator-name = "fixed-3.3V";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		regulator-boot-on;

		regulator-always-on;

	};



	vcc_sdhi0: regulator-vcc-sdhi0 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI0 Vcc";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	vccq_sdhi0: regulator-vccq-sdhi0 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI0 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;

		gpios-states = <1>;

		states = <3300000 1

			  1800000 0>;

	};



	vcc_sdhi3: regulator-vcc-sdhi3 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI3 Vcc";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	vccq_sdhi3: regulator-vccq-sdhi3 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI3 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;

		gpios-states = <1>;

		states = <3300000 1

			  1800000 0>;

	};

};



&pfc {
@@ -43,12 +110,93 @@ 
		groups = "scif_clk_a";

		function = "scif_clk";

	};



	sdhi0_pins: sd0 {

		groups = "sdhi0_data4", "sdhi0_ctrl";

		function = "sdhi0";

		power-source = <3300>;

	};



	sdhi0_pins_uhs: sd0_uhs {

		groups = "sdhi0_data4", "sdhi0_ctrl";

		function = "sdhi0";

		power-source = <1800>;

	};



	sdhi2_pins: sd2 {

		groups = "sdhi2_data8", "sdhi2_ctrl";

		function = "sdhi2";

		power-source = <3300>;

	};



	sdhi2_pins_uhs: sd2_uhs {

		groups = "sdhi2_data8", "sdhi2_ctrl";

		function = "sdhi2";

		power-source = <1800>;

	};



	sdhi3_pins: sd3 {

		groups = "sdhi3_data4", "sdhi3_ctrl";

		function = "sdhi3";

		power-source = <3300>;

	};



	sdhi3_pins_uhs: sd3_uhs {

		groups = "sdhi3_data4", "sdhi3_ctrl";

		function = "sdhi3";

		power-source = <1800>;

	};

};



&extal_clk {

	clock-frequency = <16666666>;

};



&extalr_clk {

	clock-frequency = <32768>;

};



&sdhi0 {

	pinctrl-0 = <&sdhi0_pins>;

	pinctrl-1 = <&sdhi0_pins_uhs>;

	pinctrl-names = "default", "state_uhs";



	vmmc-supply = <&vcc_sdhi0>;

	vqmmc-supply = <&vccq_sdhi0>;

	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;

	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;

	bus-width = <4>;

	sd-uhs-sdr50;

	status = "okay";

};



&sdhi2 {

	/* used for on-board 8bit eMMC */

	pinctrl-0 = <&sdhi2_pins>;

	pinctrl-1 = <&sdhi2_pins_uhs>;

	pinctrl-names = "default", "state_uhs";



	vmmc-supply = <&reg_3p3v>;

	vqmmc-supply = <&reg_1p8v>;

	bus-width = <8>;

	non-removable;

	status = "okay";

};



&sdhi3 {

	pinctrl-0 = <&sdhi3_pins>;

	pinctrl-1 = <&sdhi3_pins_uhs>;

	pinctrl-names = "default", "state_uhs";



	vmmc-supply = <&vcc_sdhi3>;

	vqmmc-supply = <&vccq_sdhi3>;

	cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;

	wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;

	bus-width = <4>;

	sd-uhs-sdr50;

	status = "okay";

};



&scif2 {

	pinctrl-0 = <&scif2_pins>;

	pinctrl-names = "default";

arch/arm64/boot/dts/renesas/r8a7796.dtsi

+139 −0
Original line number Diff line number Diff line
@@ -251,5 +251,144 @@ 
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			status = "disabled";

		};



		dmac0: dma-controller@e6700000 {

			compatible = "renesas,dmac-r8a7796",

				     "renesas,rcar-dmac";

			reg = <0 0xe6700000 0 0x10000>;

			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "error",

					"ch0", "ch1", "ch2", "ch3",

					"ch4", "ch5", "ch6", "ch7",

					"ch8", "ch9", "ch10", "ch11",

					"ch12", "ch13", "ch14", "ch15";

			clocks = <&cpg CPG_MOD 219>;

			clock-names = "fck";

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			#dma-cells = <1>;

			dma-channels = <16>;

		};



		dmac1: dma-controller@e7300000 {

			compatible = "renesas,dmac-r8a7796",

				     "renesas,rcar-dmac";

			reg = <0 0xe7300000 0 0x10000>;

			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "error",

					"ch0", "ch1", "ch2", "ch3",

					"ch4", "ch5", "ch6", "ch7",

					"ch8", "ch9", "ch10", "ch11",

					"ch12", "ch13", "ch14", "ch15";

			clocks = <&cpg CPG_MOD 218>;

			clock-names = "fck";

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			#dma-cells = <1>;

			dma-channels = <16>;

		};



		dmac2: dma-controller@e7310000 {

			compatible = "renesas,dmac-r8a7796",

				     "renesas,rcar-dmac";

			reg = <0 0xe7310000 0 0x10000>;

			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "error",

					"ch0", "ch1", "ch2", "ch3",

					"ch4", "ch5", "ch6", "ch7",

					"ch8", "ch9", "ch10", "ch11",

					"ch12", "ch13", "ch14", "ch15";

			clocks = <&cpg CPG_MOD 217>;

			clock-names = "fck";

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			#dma-cells = <1>;

			dma-channels = <16>;

		};



		sdhi0: sd@ee100000 {

			compatible = "renesas,sdhi-r8a7796";

			reg = <0 0xee100000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			status = "disabled";

		};



		sdhi1: sd@ee120000 {

			compatible = "renesas,sdhi-r8a7796";

			reg = <0 0xee120000 0 0x2000>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 313>;

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			status = "disabled";

		};



		sdhi2: sd@ee140000 {

			compatible = "renesas,sdhi-r8a7796";

			reg = <0 0xee140000 0 0x2000>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			status = "disabled";

		};



		sdhi3: sd@ee160000 {

			compatible = "renesas,sdhi-r8a7796";

			reg = <0 0xee160000 0 0x2000>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			max-frequency = <200000000>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			status = "disabled";

		};

	};

};

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