Merge branch 'mlxsw-devlink-shared-buffers' (cb689269) · Commits · 戴 / test

drivers/net/ethernet/mellanox/mlxsw/core.c

+505 −177

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/mellanox/mlxsw/core.h

+56 −0

Original line number	Original line	Diff line number	Diff line
	@@ -43,6 +43,7 @@
	#include <linux/gfp.h>		#include <linux/gfp.h>
	#include <linux/types.h>		#include <linux/types.h>
	#include <linux/skbuff.h>		#include <linux/skbuff.h>
			#include <linux/workqueue.h>
	#include <net/devlink.h>		#include <net/devlink.h>

	#include "trap.h"		#include "trap.h"
	@@ -108,6 +109,19 @@ void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core,
	const struct mlxsw_event_listener *el,		const struct mlxsw_event_listener *el,
	void *priv);		void *priv);

			typedef void mlxsw_reg_trans_cb_t(struct mlxsw_core mlxsw_core, char payload,
			size_t payload_len, unsigned long cb_priv);

			int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core,
			const struct mlxsw_reg_info reg, char payload,
			struct list_head *bulk_list,
			mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv);
			int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core,
			const struct mlxsw_reg_info reg, char payload,
			struct list_head *bulk_list,
			mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv);
			int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list);

	int mlxsw_reg_query(struct mlxsw_core *mlxsw_core,		int mlxsw_reg_query(struct mlxsw_core *mlxsw_core,
	const struct mlxsw_reg_info reg, char payload);		const struct mlxsw_reg_info reg, char payload);
	int mlxsw_reg_write(struct mlxsw_core *mlxsw_core,		int mlxsw_reg_write(struct mlxsw_core *mlxsw_core,
	@@ -137,11 +151,22 @@ struct mlxsw_core_port {
	struct devlink_port devlink_port;		struct devlink_port devlink_port;
	};		};

			static inline void *
			mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port)
			{
			/* mlxsw_core_port is ensured to always be the first field in driver
			* port structure.
			*/
			return mlxsw_core_port;
			}

	int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core,		int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core,
	struct mlxsw_core_port *mlxsw_core_port, u8 local_port,		struct mlxsw_core_port *mlxsw_core_port, u8 local_port,
	struct net_device *dev, bool split, u32 split_group);		struct net_device *dev, bool split, u32 split_group);
	void mlxsw_core_port_fini(struct mlxsw_core_port *mlxsw_core_port);		void mlxsw_core_port_fini(struct mlxsw_core_port *mlxsw_core_port);

			int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay);

	#define MLXSW_CONFIG_PROFILE_SWID_COUNT 8		#define MLXSW_CONFIG_PROFILE_SWID_COUNT 8

	struct mlxsw_swid_config {		struct mlxsw_swid_config {
	@@ -200,6 +225,37 @@ struct mlxsw_driver {
	int (port_split)(struct mlxsw_core mlxsw_core, u8 local_port,		int (port_split)(struct mlxsw_core mlxsw_core, u8 local_port,
	unsigned int count);		unsigned int count);
	int (port_unsplit)(struct mlxsw_core mlxsw_core, u8 local_port);		int (port_unsplit)(struct mlxsw_core mlxsw_core, u8 local_port);
			int (sb_pool_get)(struct mlxsw_core mlxsw_core,
			unsigned int sb_index, u16 pool_index,
			struct devlink_sb_pool_info *pool_info);
			int (sb_pool_set)(struct mlxsw_core mlxsw_core,
			unsigned int sb_index, u16 pool_index, u32 size,
			enum devlink_sb_threshold_type threshold_type);
			int (sb_port_pool_get)(struct mlxsw_core_port mlxsw_core_port,
			unsigned int sb_index, u16 pool_index,
			u32 *p_threshold);
			int (sb_port_pool_set)(struct mlxsw_core_port mlxsw_core_port,
			unsigned int sb_index, u16 pool_index,
			u32 threshold);
			int (sb_tc_pool_bind_get)(struct mlxsw_core_port mlxsw_core_port,
			unsigned int sb_index, u16 tc_index,
			enum devlink_sb_pool_type pool_type,
			u16 p_pool_index, u32 p_threshold);
			int (sb_tc_pool_bind_set)(struct mlxsw_core_port mlxsw_core_port,
			unsigned int sb_index, u16 tc_index,
			enum devlink_sb_pool_type pool_type,
			u16 pool_index, u32 threshold);
			int (sb_occ_snapshot)(struct mlxsw_core mlxsw_core,
			unsigned int sb_index);
			int (sb_occ_max_clear)(struct mlxsw_core mlxsw_core,
			unsigned int sb_index);
			int (sb_occ_port_pool_get)(struct mlxsw_core_port mlxsw_core_port,
			unsigned int sb_index, u16 pool_index,
			u32 p_cur, u32 p_max);
			int (sb_occ_tc_port_bind_get)(struct mlxsw_core_port mlxsw_core_port,
			unsigned int sb_index, u16 tc_index,
			enum devlink_sb_pool_type pool_type,
			u32 p_cur, u32 p_max);
	void (txhdr_construct)(struct sk_buff skb,		void (txhdr_construct)(struct sk_buff skb,
	const struct mlxsw_tx_info *tx_info);		const struct mlxsw_tx_info *tx_info);
	u8 txhdr_len;		u8 txhdr_len;

drivers/net/ethernet/mellanox/mlxsw/reg.h

+134 −1

Original line number	Original line	Diff line number	Diff line
	@@ -3566,6 +3566,10 @@ MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
	*/		*/
	MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);		MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);

			/* shared max_buff limits for dynamic threshold for SBCM, SBPM */
			#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
			#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14

	/* reg_sbcm_max_buff		/* reg_sbcm_max_buff
	* When the pool associated to the port-pg/tclass is configured to		* When the pool associated to the port-pg/tclass is configured to
	* static, Maximum buffer size for the limiter configured in cells.		* static, Maximum buffer size for the limiter configured in cells.
	@@ -3632,6 +3636,27 @@ MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
	*/		*/
	MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);		MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);

			/* reg_sbpm_buff_occupancy
			* Current buffer occupancy in cells.
			* Access: RO
			*/
			MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);

			/* reg_sbpm_clr
			* Clear Max Buffer Occupancy
			* When this bit is set, max_buff_occupancy field is cleared (and a
			* new max value is tracked from the time the clear was performed).
			* Access: OP
			*/
			MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);

			/* reg_sbpm_max_buff_occupancy
			* Maximum value of buffer occupancy in cells monitored. Cleared by
			* writing to the clr field.
			* Access: RO
			*/
			MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);

	/* reg_sbpm_min_buff		/* reg_sbpm_min_buff
	* Minimum buffer size for the limiter, in cells.		* Minimum buffer size for the limiter, in cells.
	* Access: RW		* Access: RW
	@@ -3652,17 +3677,25 @@ MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
	MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);		MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);

	static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,		static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
	enum mlxsw_reg_sbxx_dir dir,		enum mlxsw_reg_sbxx_dir dir, bool clr,
	u32 min_buff, u32 max_buff)		u32 min_buff, u32 max_buff)
	{		{
	MLXSW_REG_ZERO(sbpm, payload);		MLXSW_REG_ZERO(sbpm, payload);
	mlxsw_reg_sbpm_local_port_set(payload, local_port);		mlxsw_reg_sbpm_local_port_set(payload, local_port);
	mlxsw_reg_sbpm_pool_set(payload, pool);		mlxsw_reg_sbpm_pool_set(payload, pool);
	mlxsw_reg_sbpm_dir_set(payload, dir);		mlxsw_reg_sbpm_dir_set(payload, dir);
			mlxsw_reg_sbpm_clr_set(payload, clr);
	mlxsw_reg_sbpm_min_buff_set(payload, min_buff);		mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
	mlxsw_reg_sbpm_max_buff_set(payload, max_buff);		mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
	}		}

			static inline void mlxsw_reg_sbpm_unpack(char payload, u32 p_buff_occupancy,
			u32 *p_max_buff_occupancy)
			{
			*p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
			*p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
			}

	/* SBMM - Shared Buffer Multicast Management Register		/* SBMM - Shared Buffer Multicast Management Register
	* --------------------------------------------------		* --------------------------------------------------
	* The SBMM register configures and retrieves the shared buffer allocation		* The SBMM register configures and retrieves the shared buffer allocation
	@@ -3718,6 +3751,104 @@ static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
	mlxsw_reg_sbmm_pool_set(payload, pool);		mlxsw_reg_sbmm_pool_set(payload, pool);
	}		}

			/* SBSR - Shared Buffer Status Register
			* ------------------------------------
			* The SBSR register retrieves the shared buffer occupancy according to
			* Port-Pool. Note that this register enables reading a large amount of data.
			* It is the user's responsibility to limit the amount of data to ensure the
			* response can match the maximum transfer unit. In case the response exceeds
			* the maximum transport unit, it will be truncated with no special notice.
			*/
			#define MLXSW_REG_SBSR_ID 0xB005
			#define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
			#define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
			#define MLXSW_REG_SBSR_REC_MAX_COUNT 120
			#define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
			MLXSW_REG_SBSR_REC_LEN * \
			MLXSW_REG_SBSR_REC_MAX_COUNT)

			static const struct mlxsw_reg_info mlxsw_reg_sbsr = {
			.id = MLXSW_REG_SBSR_ID,
			.len = MLXSW_REG_SBSR_LEN,
			};

			/* reg_sbsr_clr
			* Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
			* field is cleared (and a new max value is tracked from the time the clear
			* was performed).
			* Access: OP
			*/
			MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);

			/* reg_sbsr_ingress_port_mask
			* Bit vector for all ingress network ports.
			* Indicates which of the ports (for which the relevant bit is set)
			* are affected by the set operation. Configuration of any other port
			* does not change.
			* Access: Index
			*/
			MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);

			/* reg_sbsr_pg_buff_mask
			* Bit vector for all switch priority groups.
			* Indicates which of the priorities (for which the relevant bit is set)
			* are affected by the set operation. Configuration of any other priority
			* does not change.
			* Range is 0..cap_max_pg_buffers - 1
			* Access: Index
			*/
			MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);

			/* reg_sbsr_egress_port_mask
			* Bit vector for all egress network ports.
			* Indicates which of the ports (for which the relevant bit is set)
			* are affected by the set operation. Configuration of any other port
			* does not change.
			* Access: Index
			*/
			MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);

			/* reg_sbsr_tclass_mask
			* Bit vector for all traffic classes.
			* Indicates which of the traffic classes (for which the relevant bit is
			* set) are affected by the set operation. Configuration of any other
			* traffic class does not change.
			* Range is 0..cap_max_tclass - 1
			* Access: Index
			*/
			MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);

			static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
			{
			MLXSW_REG_ZERO(sbsr, payload);
			mlxsw_reg_sbsr_clr_set(payload, clr);
			}

			/* reg_sbsr_rec_buff_occupancy
			* Current buffer occupancy in cells.
			* Access: RO
			*/
			MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
			0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);

			/* reg_sbsr_rec_max_buff_occupancy
			* Maximum value of buffer occupancy in cells monitored. Cleared by
			* writing to the clr field.
			* Access: RO
			*/
			MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
			0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);

			static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
			u32 *p_buff_occupancy,
			u32 *p_max_buff_occupancy)
			{
			*p_buff_occupancy =
			mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
			*p_max_buff_occupancy =
			mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
			}

	static inline const char *mlxsw_reg_id_str(u16 reg_id)		static inline const char *mlxsw_reg_id_str(u16 reg_id)
	{		{
	switch (reg_id) {		switch (reg_id) {
	@@ -3813,6 +3944,8 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id)
	return "SBPM";		return "SBPM";
	case MLXSW_REG_SBMM_ID:		case MLXSW_REG_SBMM_ID:
	return "SBMM";		return "SBMM";
			case MLXSW_REG_SBSR_ID:
			return "SBSR";
	default:		default:
	return "UNKNOWN";		return "UNKNOWN";
	}		}

drivers/net/ethernet/mellanox/mlxsw/spectrum.c

+22 −10

Original line number	Original line	Diff line number	Diff line
	@@ -2434,6 +2434,7 @@ static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,

	err_switchdev_init:		err_switchdev_init:
	err_lag_init:		err_lag_init:
			mlxsw_sp_buffers_fini(mlxsw_sp);
	err_buffers_init:		err_buffers_init:
	err_flood_init:		err_flood_init:
	mlxsw_sp_traps_fini(mlxsw_sp);		mlxsw_sp_traps_fini(mlxsw_sp);
	@@ -2448,6 +2449,7 @@ static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
	{		{
	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);		struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);

			mlxsw_sp_buffers_fini(mlxsw_sp);
	mlxsw_sp_switchdev_fini(mlxsw_sp);		mlxsw_sp_switchdev_fini(mlxsw_sp);
	mlxsw_sp_traps_fini(mlxsw_sp);		mlxsw_sp_traps_fini(mlxsw_sp);
	mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);		mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
	@@ -2498,6 +2500,16 @@ static struct mlxsw_driver mlxsw_sp_driver = {
	.fini = mlxsw_sp_fini,		.fini = mlxsw_sp_fini,
	.port_split = mlxsw_sp_port_split,		.port_split = mlxsw_sp_port_split,
	.port_unsplit = mlxsw_sp_port_unsplit,		.port_unsplit = mlxsw_sp_port_unsplit,
			.sb_pool_get = mlxsw_sp_sb_pool_get,
			.sb_pool_set = mlxsw_sp_sb_pool_set,
			.sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
			.sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
			.sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
			.sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
			.sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
			.sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
			.sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
			.sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
	.txhdr_construct = mlxsw_sp_txhdr_construct,		.txhdr_construct = mlxsw_sp_txhdr_construct,
	.txhdr_len = MLXSW_TXHDR_LEN,		.txhdr_len = MLXSW_TXHDR_LEN,
	.profile = &mlxsw_sp_config_profile,		.profile = &mlxsw_sp_config_profile,

drivers/net/ethernet/mellanox/mlxsw/spectrum.h

+68 −0

Original line number	Original line	Diff line number	Diff line
	@@ -65,6 +65,7 @@
	#define MLXSW_SP_BYTES_PER_CELL 96		#define MLXSW_SP_BYTES_PER_CELL 96

	#define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)		#define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
			#define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)

	/* Maximum delay buffer needed in case of PAUSE frames, in cells.		/* Maximum delay buffer needed in case of PAUSE frames, in cells.
	* Assumes 100m cable and maximum MTU.		* Assumes 100m cable and maximum MTU.
	@@ -117,6 +118,40 @@ static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
	return fid >= MLXSW_SP_VFID_BASE;		return fid >= MLXSW_SP_VFID_BASE;
	}		}

			struct mlxsw_sp_sb_pr {
			enum mlxsw_reg_sbpr_mode mode;
			u32 size;
			};

			struct mlxsw_cp_sb_occ {
			u32 cur;
			u32 max;
			};

			struct mlxsw_sp_sb_cm {
			u32 min_buff;
			u32 max_buff;
			u8 pool;
			struct mlxsw_cp_sb_occ occ;
			};

			struct mlxsw_sp_sb_pm {
			u32 min_buff;
			u32 max_buff;
			struct mlxsw_cp_sb_occ occ;
			};

			#define MLXSW_SP_SB_POOL_COUNT 4
			#define MLXSW_SP_SB_TC_COUNT 8

			struct mlxsw_sp_sb {
			struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
			struct {
			struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
			struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
			} ports[MLXSW_PORT_MAX_PORTS];
			};

	struct mlxsw_sp {		struct mlxsw_sp {
	struct {		struct {
	struct list_head list;		struct list_head list;
	@@ -147,6 +182,7 @@ struct mlxsw_sp {
	struct mlxsw_sp_upper master_bridge;		struct mlxsw_sp_upper master_bridge;
	struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];		struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
	u8 port_to_module[MLXSW_PORT_MAX_PORTS];		u8 port_to_module[MLXSW_PORT_MAX_PORTS];
			struct mlxsw_sp_sb sb;
	};		};

	static inline struct mlxsw_sp_upper *		static inline struct mlxsw_sp_upper *
	@@ -277,7 +313,39 @@ enum mlxsw_sp_flood_table {
	};		};

	int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);		int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
			void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
	int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);		int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
			int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
			unsigned int sb_index, u16 pool_index,
			struct devlink_sb_pool_info *pool_info);
			int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
			unsigned int sb_index, u16 pool_index, u32 size,
			enum devlink_sb_threshold_type threshold_type);
			int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
			unsigned int sb_index, u16 pool_index,
			u32 *p_threshold);
			int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
			unsigned int sb_index, u16 pool_index,
			u32 threshold);
			int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
			unsigned int sb_index, u16 tc_index,
			enum devlink_sb_pool_type pool_type,
			u16 p_pool_index, u32 p_threshold);
			int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
			unsigned int sb_index, u16 tc_index,
			enum devlink_sb_pool_type pool_type,
			u16 pool_index, u32 threshold);
			int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
			unsigned int sb_index);
			int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
			unsigned int sb_index);
			int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
			unsigned int sb_index, u16 pool_index,
			u32 p_cur, u32 p_max);
			int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
			unsigned int sb_index, u16 tc_index,
			enum devlink_sb_pool_type pool_type,
			u32 p_cur, u32 p_max);

	int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);		int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
	void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);		void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);

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