Merge branch 'features/imx3' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc (cb66bb1d) · Commits · 戴 / test

arch/arm/mach-imx/Makefile

+2 −2

Original line number	Diff line number	Diff line
		@@ -8,8 +8,8 @@ obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
		obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
		obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o

		obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
		obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
		obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
		obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o pm-imx3.o

		obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o

+1 −0

Original line number	Diff line number	Diff line
		@@ -64,6 +64,7 @@
		#define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21)
		#define MXC_CCM_CCMR_LPM_OFFSET 14
		#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
		#define MXC_CCM_CCMR_LPM_WAIT_MX35 (0x1 << 14)
		#define MXC_CCM_CCMR_FIRS_OFFSET 11
		#define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11)
		#define MXC_CCM_CCMR_UPE (1 << 9)

+5 −0

Original line number	Diff line number	Diff line
		@@ -34,6 +34,8 @@ static void imx3_idle(void)
		{
		unsigned long reg = 0;

		mx3_cpu_lp_set(MX3_WAIT);

		__asm__ __volatile__(
		/* disable I and D cache */
		"mrc p15, 0, %0, c1, c0, 0\n"
		@@ -173,6 +175,9 @@ void __init imx31_soc_init(void)
		}

		imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);

		imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
		imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
		}
		#endif /* ifdef CONFIG_SOC_IMX31 */

0 → 100644

+37 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
		*
		* The code contained herein is licensed under the GNU General Public
		* License. You may obtain a copy of the GNU General Public License
		* Version 2 or later at the following locations:
		*
		* http://www.opensource.org/licenses/gpl-license.html
		* http://www.gnu.org/copyleft/gpl.html
		*/
		#include <linux/io.h>
		#include <mach/common.h>
		#include <mach/hardware.h>
		#include <mach/devices-common.h>
		#include "crmregs-imx3.h"

		/*
		* Set cpu low power mode before WFI instruction. This function is called
		* mx3 because it can be used for mx31 and mx35.
		* Currently only WAIT_MODE is supported.
		*/
		void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
		{
		int reg = __raw_readl(MXC_CCM_CCMR);
		reg &= ~MXC_CCM_CCMR_LPM_MASK;

		switch (mode) {
		case MX3_WAIT:
		if (cpu_is_mx35())
		reg \|= MXC_CCM_CCMR_LPM_WAIT_MX35;
		__raw_writel(reg, MXC_CCM_CCMR);
		break;
		default:
		pr_err("Unknown cpu power mode: %d\n", mode);
		return;
		}
		}

+24 −0

Original line number	Diff line number	Diff line

		#include <linux/module.h>
		#include <linux/io.h>
		#include <mach/hardware.h>

		unsigned int __mxc_cpu_type;
		@@ -18,3 +19,26 @@ void imx_print_silicon_rev(const char *cpu, int srev)
		pr_info("CPU identified as %s, silicon rev %d.%d\n",
		cpu, (srev >> 4) & 0xf, srev & 0xf);
		}

		void __init imx_set_aips(void __iomem *base)
		{
		unsigned int reg;
		/*
		* Set all MPROTx to be non-bufferable, trusted for R/W,
		* not forced to user-mode.
		*/
		__raw_writel(0x77777777, base + 0x0);
		__raw_writel(0x77777777, base + 0x4);

		/*
		* Set all OPACRx to be non-bufferable, to not require
		* supervisor privilege level for access, allow for
		* write access and untrusted master access.
		*/
		__raw_writel(0x0, base + 0x40);
		__raw_writel(0x0, base + 0x44);
		__raw_writel(0x0, base + 0x48);
		__raw_writel(0x0, base + 0x4C);
		reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
		__raw_writel(reg, base + 0x50);
		}