Unverified Commit cb54fbd2 authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard
Browse files

clk: sunxi-ng: Add maximum rate constraint to NM PLLs 



On some NM PLLs, frequency can be set above PLL working range.

Add a constraint for maximum supported rate. This way, drivers can
specify which is maximum allowed rate for PLL.

Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent 58c0f798

drivers/clk/sunxi-ng/ccu_nm.c

+7 −0
Original line number Diff line number Diff line
@@ -124,6 +124,13 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate, 
		return rate;

	}



	if (nm->max_rate && rate > nm->max_rate) {

		rate = nm->max_rate;

		if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)

			rate /= nm->fixed_post_div;

		return rate;

	}



	if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {

		if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)

			rate /= nm->fixed_post_div;

drivers/clk/sunxi-ng/ccu_nm.h

+30 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ struct ccu_nm { 


	unsigned int		fixed_post_div;

	unsigned int		min_rate;

	unsigned int		max_rate;



	struct ccu_common	common;

};
@@ -115,6 +116,35 @@ struct ccu_nm { 
		},							\

	}



#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name,	\

						 _parent, _reg,		\

						 _min_rate, _max_rate,	\

						 _nshift, _nwidth,	\

						 _mshift, _mwidth,	\

						 _frac_en, _frac_sel,	\

						 _frac_rate_0,		\

						 _frac_rate_1,		\

						 _gate, _lock, _flags)	\

	struct ccu_nm _struct = {					\

		.enable		= _gate,				\

		.lock		= _lock,				\

		.n		= _SUNXI_CCU_MULT(_nshift, _nwidth),	\

		.m		= _SUNXI_CCU_DIV(_mshift, _mwidth),	\

		.frac		= _SUNXI_CCU_FRAC(_frac_en, _frac_sel,	\

						  _frac_rate_0,		\

						  _frac_rate_1),	\

		.min_rate	= _min_rate,				\

		.max_rate	= _max_rate,				\

		.common		= {					\

			.reg		= _reg,				\

			.features	= CCU_FEATURE_FRACTIONAL,	\

			.hw.init	= CLK_HW_INIT(_name,		\

						      _parent,		\

						      &ccu_nm_ops,	\

						      _flags),		\

		},							\

	}



#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg,	\

				    _nshift, _nwidth,			\

				    _mshift, _mwidth,			\

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