mtd: spi-nor: Move SFDP logic out of the core

# SPDX-License-Identifier: GPL-2.0

spi-nor-objs			:= core.o

spi-nor-objs			:= core.o sfdp.o

obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2005, Intec Automation Inc.

 * Copyright (C) 2014, Freescale Semiconductor, Inc.

 */

#ifndef __LINUX_MTD_SPI_NOR_INTERNAL_H

#define __LINUX_MTD_SPI_NOR_INTERNAL_H

#include "sfdp.h"

int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);

int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);

int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);

ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,

			  u8 *buf);

int spi_nor_hwcaps_read2cmd(u32 hwcaps);

u8 spi_nor_convert_3to4_read(u8 opcode);

void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,

			     enum spi_nor_protocol proto);

void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,

			    u8 opcode);

struct spi_nor_erase_region *

spi_nor_region_next(struct spi_nor_erase_region *region);

void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,

				    u8 erase_mask, u64 flash_size);

int spi_nor_post_bfpt_fixups(struct spi_nor *nor,

			     const struct sfdp_parameter_header *bfpt_header,

			     const struct sfdp_bfpt *bfpt,

			     struct spi_nor_flash_parameter *params);

#endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2005, Intec Automation Inc.

 * Copyright (C) 2014, Freescale Semiconductor, Inc.

 */

#ifndef __LINUX_MTD_SFDP_H

#define __LINUX_MTD_SFDP_H

/* Basic Flash Parameter Table */

/*

 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.

 * They are indexed from 1 but C arrays are indexed from 0.

 */

#define BFPT_DWORD(i)		((i) - 1)

#define BFPT_DWORD_MAX		16

struct sfdp_bfpt {

	u32	dwords[BFPT_DWORD_MAX];

};

/* The first version of JESD216 defined only 9 DWORDs. */

#define BFPT_DWORD_MAX_JESD216			9

/* 1st DWORD. */

#define BFPT_DWORD1_FAST_READ_1_1_2		BIT(16)

#define BFPT_DWORD1_ADDRESS_BYTES_MASK		GENMASK(18, 17)

#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY	(0x0UL << 17)

#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4	(0x1UL << 17)

#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY	(0x2UL << 17)

#define BFPT_DWORD1_DTR				BIT(19)

#define BFPT_DWORD1_FAST_READ_1_2_2		BIT(20)

#define BFPT_DWORD1_FAST_READ_1_4_4		BIT(21)

#define BFPT_DWORD1_FAST_READ_1_1_4		BIT(22)

/* 5th DWORD. */

#define BFPT_DWORD5_FAST_READ_2_2_2		BIT(0)

#define BFPT_DWORD5_FAST_READ_4_4_4		BIT(4)

/* 11th DWORD. */

#define BFPT_DWORD11_PAGE_SIZE_SHIFT		4

#define BFPT_DWORD11_PAGE_SIZE_MASK		GENMASK(7, 4)

/* 15th DWORD. */

/*

 * (from JESD216 rev B)

 * Quad Enable Requirements (QER):

 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4

 *         reads based on instruction. DQ3/HOLD# functions are hold during

 *         instruction phase.

 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with

 *         two data bytes where bit 1 of the second byte is one.

 *         [...]

 *         Writing only one byte to the status register has the side-effect of

 *         clearing status register 2, including the QE bit. The 100b code is

 *         used if writing one byte to the status register does not modify

 *         status register 2.

 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with

 *         one data byte where bit 6 is one.

 *         [...]

 * - 011b: QE is bit 7 of status register 2. It is set via Write status

 *         register 2 instruction 3Eh with one data byte where bit 7 is one.

 *         [...]

 *         The status register 2 is read using instruction 3Fh.

 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with

 *         two data bytes where bit 1 of the second byte is one.

 *         [...]

 *         In contrast to the 001b code, writing one byte to the status

 *         register does not modify status register 2.

 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using

 *         Read Status instruction 05h. Status register2 is read using

 *         instruction 35h. QE is set via Write Status instruction 01h with

 *         two data bytes where bit 1 of the second byte is one.

 *         [...]

 */

#define BFPT_DWORD15_QER_MASK			GENMASK(22, 20)

#define BFPT_DWORD15_QER_NONE			(0x0UL << 20) /* Micron */

#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY		(0x1UL << 20)

#define BFPT_DWORD15_QER_SR1_BIT6		(0x2UL << 20) /* Macronix */

#define BFPT_DWORD15_QER_SR2_BIT7		(0x3UL << 20)

#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD		(0x4UL << 20)

#define BFPT_DWORD15_QER_SR2_BIT1		(0x5UL << 20) /* Spansion */

struct sfdp_parameter_header {

	u8		id_lsb;

	u8		minor;

	u8		major;

	u8		length; /* in double words */

	u8		parameter_table_pointer[3]; /* byte address */

	u8		id_msb;

};

int spi_nor_parse_sfdp(struct spi_nor *nor,

		       struct spi_nor_flash_parameter *params);

#endif /* __LINUX_MTD_SFDP_H */