Commit cb2808da authored by Colin Xu's avatar Colin Xu Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Fix vGPU CSFE_CHICKEN1_REG mmio handler 



Enter failsafe if vgpu tries to change CSFE_CHICKEN1_REG setting
which is controlled by host.

Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarColin Xu <colin.xu@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 888c0094

drivers/gpu/drm/i915/gvt/handlers.c

+19 −1
Original line number Diff line number Diff line
@@ -1789,6 +1789,21 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 
	return 0;

}



static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,

				    unsigned int offset, void *p_data,

				    unsigned int bytes)

{

	u32 data = *(u32 *)p_data;



	(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);

	write_vreg(vgpu, offset, p_data, bytes);



	if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8))

		enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);



	return 0;

}



#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \

	ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \

		f, s, am, rm, d, r, w); \
@@ -3075,7 +3090,10 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) 
	MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);



	MMIO_D(_MMIO(0x44500), D_SKL_PLUS);

	MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);

#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)

	MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,

		      NULL, csfe_chicken1_mmio_write);

#undef CSFE_CHICKEN1_REG

	MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,

		 NULL, NULL);

	MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,

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