Commit cb0fb271 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'imx-drm-next-2015-10-30' of git://git.pengutronix.de/git/pza/linux into drm-next 

imx-drm fixes and color format updates

- Some correctness fixes found by coccinelle
- Add drivers/gpu/ipu-v3 directory to MAINTAINERS
- Add support for more color formats
- Fix a regression, making displays larger than FullHD work again

* tag 'imx-drm-next-2015-10-30' of git://git.pengutronix.de/git/pza/linux:
  drm/imx: hdmi: fix HDMI setup to allow modes larger than FullHD
  gpu: ipu-v3: fix div_ratio type
  gpu: ipu-v3: csi: add support for 8 bpp grayscale sensors.
  drm/imx: enable ARGB4444 16-bit color format
  gpu: ipu-v3: add support for ARGB4444 16-bit color format
  drm/imx: ipuv3-plane: enable support for RGBX8888 and RGBA8888 pixel formats
  gpu: ipu-v3: add support for RGBX8888 and RGBA8888 pixel formats
  drm/imx: enable 15-bit RGB with 1-bit alpha formats
  gpu: ipu-v3: add support for 15-bit RGB with 1-bit alpha formats
  MAINTAINERS: Add IPUv3 core driver to the i.MX DRM driver section
  gpu: ipu-v3: ipu-csi: bool test doesn't need a comparison to false
parents 793423ff a5f4185c

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -3618,6 +3618,7 @@ M: Philipp Zabel <p.zabel@pengutronix.de> 
L:	dri-devel@lists.freedesktop.org

S:	Maintained

F:	drivers/gpu/drm/imx/

F:	drivers/gpu/ipu-v3/

F:	Documentation/devicetree/bindings/drm/imx/



DRM DRIVERS FOR NVIDIA TEGRA

drivers/gpu/drm/imx/dw_hdmi-imx.c

+12 −4
Original line number Diff line number Diff line
@@ -48,11 +48,17 @@ static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = { 
			{ 0x40a2, 0x000a },

		},

	}, {

		~0UL, {

		216000000, {

			{ 0x00a0, 0x000a },

			{ 0x2001, 0x000f },

			{ 0x4002, 0x000f },

		},

	}, {

		~0UL, {

			{ 0x0000, 0x0000 },

			{ 0x0000, 0x0000 },

			{ 0x0000, 0x0000 },

		},

	}

};
@@ -82,7 +88,7 @@ static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = { 
 */

static const struct dw_hdmi_phy_config imx_phy_config[] = {

	/*pixelclk   symbol   term   vlev */

	{ 148500000, 0x800d, 0x0005, 0x01ad},

	{ 216000000, 0x800d, 0x0005, 0x01ad},

	{ ~0UL,      0x0000, 0x0000, 0x0000}

};
@@ -148,7 +154,8 @@ static enum drm_mode_status imx6q_hdmi_mode_valid(struct drm_connector *con, 
{

	if (mode->clock < 13500)

		return MODE_CLOCK_LOW;

	if (mode->clock > 266000)

	/* FIXME: Hardware is capable of 266MHz, but setup data is missing. */

	if (mode->clock > 216000)

		return MODE_CLOCK_HIGH;



	return MODE_OK;
@@ -159,7 +166,8 @@ static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con, 
{

	if (mode->clock < 13500)

		return MODE_CLOCK_LOW;

	if (mode->clock > 270000)

	/* FIXME: Hardware is capable of 270MHz, but setup data is missing. */

	if (mode->clock > 216000)

		return MODE_CLOCK_HIGH;



	return MODE_OK;

drivers/gpu/drm/imx/ipuv3-plane.c

+16 −0
Original line number Diff line number Diff line
@@ -23,12 +23,21 @@ 
#define to_ipu_plane(x)	container_of(x, struct ipu_plane, base)



static const uint32_t ipu_plane_formats[] = {

	DRM_FORMAT_ARGB1555,

	DRM_FORMAT_XRGB1555,

	DRM_FORMAT_ABGR1555,

	DRM_FORMAT_XBGR1555,

	DRM_FORMAT_RGBA5551,

	DRM_FORMAT_BGRA5551,

	DRM_FORMAT_ARGB4444,

	DRM_FORMAT_ARGB8888,

	DRM_FORMAT_XRGB8888,

	DRM_FORMAT_ABGR8888,

	DRM_FORMAT_XBGR8888,

	DRM_FORMAT_RGBA8888,

	DRM_FORMAT_RGBX8888,

	DRM_FORMAT_BGRA8888,

	DRM_FORMAT_BGRA8888,

	DRM_FORMAT_YUYV,

	DRM_FORMAT_YVYU,

	DRM_FORMAT_YUV420,
@@ -175,8 +184,15 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc, 
		ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);

		/* Enable local alpha on partial plane */

		switch (fb->pixel_format) {

		case DRM_FORMAT_ARGB1555:

		case DRM_FORMAT_ABGR1555:

		case DRM_FORMAT_RGBA5551:

		case DRM_FORMAT_BGRA5551:

		case DRM_FORMAT_ARGB4444:

		case DRM_FORMAT_ARGB8888:

		case DRM_FORMAT_ABGR8888:

		case DRM_FORMAT_RGBA8888:

		case DRM_FORMAT_BGRA8888:

			ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);

			break;

		default:

drivers/gpu/ipu-v3/ipu-common.c

+5 −0
Original line number Diff line number Diff line
@@ -57,10 +57,15 @@ EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update); 
enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)

{

	switch (drm_fourcc) {

	case DRM_FORMAT_ARGB1555:

	case DRM_FORMAT_ABGR1555:

	case DRM_FORMAT_RGBA5551:

	case DRM_FORMAT_BGRA5551:

	case DRM_FORMAT_RGB565:

	case DRM_FORMAT_BGR565:

	case DRM_FORMAT_RGB888:

	case DRM_FORMAT_BGR888:

	case DRM_FORMAT_ARGB4444:

	case DRM_FORMAT_XRGB8888:

	case DRM_FORMAT_XBGR8888:

	case DRM_FORMAT_RGBX8888:

drivers/gpu/ipu-v3/ipu-cpmem.c

+83 −4
Original line number Diff line number Diff line
@@ -452,7 +452,7 @@ void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch, 
}

EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);



static const struct ipu_rgb def_rgb_32 = {

static const struct ipu_rgb def_xrgb_32 = {

	.red	= { .offset = 16, .length = 8, },

	.green	= { .offset =  8, .length = 8, },

	.blue	= { .offset =  0, .length = 8, },
@@ -460,7 +460,7 @@ static const struct ipu_rgb def_rgb_32 = { 
	.bits_per_pixel = 32,

};



static const struct ipu_rgb def_bgr_32 = {

static const struct ipu_rgb def_xbgr_32 = {

	.red	= { .offset =  0, .length = 8, },

	.green	= { .offset =  8, .length = 8, },

	.blue	= { .offset = 16, .length = 8, },
@@ -468,6 +468,22 @@ static const struct ipu_rgb def_bgr_32 = { 
	.bits_per_pixel = 32,

};



static const struct ipu_rgb def_rgbx_32 = {

	.red	= { .offset = 24, .length = 8, },

	.green	= { .offset = 16, .length = 8, },

	.blue	= { .offset =  8, .length = 8, },

	.transp = { .offset =  0, .length = 8, },

	.bits_per_pixel = 32,

};



static const struct ipu_rgb def_bgrx_32 = {

	.red	= { .offset =  8, .length = 8, },

	.green	= { .offset = 16, .length = 8, },

	.blue	= { .offset = 24, .length = 8, },

	.transp = { .offset =  0, .length = 8, },

	.bits_per_pixel = 32,

};



static const struct ipu_rgb def_rgb_24 = {

	.red	= { .offset = 16, .length = 8, },

	.green	= { .offset =  8, .length = 8, },
@@ -500,6 +516,46 @@ static const struct ipu_rgb def_bgr_16 = { 
	.bits_per_pixel = 16,

};



static const struct ipu_rgb def_argb_16 = {

	.red	= { .offset = 10, .length = 5, },

	.green	= { .offset =  5, .length = 5, },

	.blue	= { .offset =  0, .length = 5, },

	.transp = { .offset = 15, .length = 1, },

	.bits_per_pixel = 16,

};



static const struct ipu_rgb def_argb_16_4444 = {

	.red	= { .offset =  8, .length = 4, },

	.green	= { .offset =  4, .length = 4, },

	.blue	= { .offset =  0, .length = 4, },

	.transp = { .offset = 12, .length = 4, },

	.bits_per_pixel = 16,

};



static const struct ipu_rgb def_abgr_16 = {

	.red	= { .offset =  0, .length = 5, },

	.green	= { .offset =  5, .length = 5, },

	.blue	= { .offset = 10, .length = 5, },

	.transp = { .offset = 15, .length = 1, },

	.bits_per_pixel = 16,

};



static const struct ipu_rgb def_rgba_16 = {

	.red	= { .offset = 11, .length = 5, },

	.green	= { .offset =  6, .length = 5, },

	.blue	= { .offset =  1, .length = 5, },

	.transp = { .offset =  0, .length = 1, },

	.bits_per_pixel = 16,

};



static const struct ipu_rgb def_bgra_16 = {

	.red	= { .offset =  1, .length = 5, },

	.green	= { .offset =  6, .length = 5, },

	.blue	= { .offset = 11, .length = 5, },

	.transp = { .offset =  0, .length = 1, },

	.bits_per_pixel = 16,

};



#define Y_OFFSET(pix, x, y)	((x) + pix->width * (y))

#define U_OFFSET(pix, x, y)	((pix->width * pix->height) +		\

				 (pix->width * (y) / 4) + (x) / 2)
@@ -563,11 +619,19 @@ int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc) 
		break;

	case DRM_FORMAT_ABGR8888:

	case DRM_FORMAT_XBGR8888:

		ipu_cpmem_set_format_rgb(ch, &def_bgr_32);

		ipu_cpmem_set_format_rgb(ch, &def_xbgr_32);

		break;

	case DRM_FORMAT_ARGB8888:

	case DRM_FORMAT_XRGB8888:

		ipu_cpmem_set_format_rgb(ch, &def_rgb_32);

		ipu_cpmem_set_format_rgb(ch, &def_xrgb_32);

		break;

	case DRM_FORMAT_RGBA8888:

	case DRM_FORMAT_RGBX8888:

		ipu_cpmem_set_format_rgb(ch, &def_rgbx_32);

		break;

	case DRM_FORMAT_BGRA8888:

	case DRM_FORMAT_BGRX8888:

		ipu_cpmem_set_format_rgb(ch, &def_bgrx_32);

		break;

	case DRM_FORMAT_BGR888:

		ipu_cpmem_set_format_rgb(ch, &def_bgr_24);
@@ -581,6 +645,21 @@ int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc) 
	case DRM_FORMAT_BGR565:

		ipu_cpmem_set_format_rgb(ch, &def_bgr_16);

		break;

	case DRM_FORMAT_ARGB1555:

		ipu_cpmem_set_format_rgb(ch, &def_argb_16);

		break;

	case DRM_FORMAT_ABGR1555:

		ipu_cpmem_set_format_rgb(ch, &def_abgr_16);

		break;

	case DRM_FORMAT_RGBA5551:

		ipu_cpmem_set_format_rgb(ch, &def_rgba_16);

		break;

	case DRM_FORMAT_BGRA5551:

		ipu_cpmem_set_format_rgb(ch, &def_bgra_16);

		break;

	case DRM_FORMAT_ARGB4444:

		ipu_cpmem_set_format_rgb(ch, &def_argb_16_4444);

		break;

	default:

		return -EINVAL;

	}

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