Unverified Commit caed1d1b authored by Huacai Chen's avatar Huacai Chen Committed by Paul Burton
Browse files

MIPS: Loongson: Unify LOONGSON3/LOONGSON64 Kconfig usage 



There are mixed LOONGSON3/LOONGSON64 usages in recently changes, let's
establish some rules:

1, In Kconfig symbols, we only use CPU_LOONGSON64, MACH_LOONGSON64 and
SYS_HAS_CPU_LOONGSON64, all other derived symbols use "LOONGSON3" since
they all not widely-used symbols and sometimes not suitable for all
64-bit Loongson processors. E.g., we use symbols LOONGSON3_ENHANCEMENT,
CPU_LOONGSON3_WORKAROUNDS, etc.

2, Hide GSx64/GSx64E in Kconfig title since it is not useful for
general users. However, in the full description we use a more detailed
manner. E.g., GS264/GS464/GS464E/GS464V.

All Kconfig titles and descriptions of Loongson processors and machines
have also been updated in this patch for consistency.

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarPaul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@linux-mips.org
Cc: linux-mips@vger.kernel.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhuacai@gmail.com>
parent b2afb64c

arch/mips/Kconfig

+21 −14
Original line number Diff line number Diff line
@@ -444,7 +444,7 @@ config LASAT 
	select SYS_SUPPORTS_LITTLE_ENDIAN



config MACH_LOONGSON32

	bool "Loongson-1 family of machines"

	bool "Loongson 32-bit family of machines"

	select SYS_SUPPORTS_ZBOOT

	help

	  This enables support for the Loongson-1 family of machines.
@@ -460,7 +460,7 @@ config MACH_LOONGSON2EF 
	  This enables the support of early Loongson-2E/F family of machines.



config MACH_LOONGSON64

	bool "Loongson-2/3 GSx64 family of machines"

	bool "Loongson 64-bit family of machines"

	select ARCH_SPARSEMEM_ENABLE

	select ARCH_MIGHT_HAVE_PC_PARPORT

	select ARCH_MIGHT_HAVE_PC_SERIO
@@ -489,8 +489,12 @@ config MACH_LOONGSON64 
	select ZONE_DMA32

	select NUMA

	help

	  This enables the support of Loongson-2/3 family of processors with

	  GSx64 microarchitecture.

	  This enables the support of Loongson-2/3 family of machines.



	  Loongson-2 and Loongson-3 are 64-bit general-purpose processors with

	  GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E

	  and Loongson-2F which will be removed), developed by the Institute

	  of Computing Technology (ICT), Chinese Academy of Sciences (CAS).



config MACH_PISTACHIO

	bool "IMG Pistachio SoC based boards"
@@ -1432,7 +1436,7 @@ choice 
	default CPU_R4X00



config CPU_LOONGSON64

	bool "Loongson GSx64 CPU"

	bool "Loongson 64-bit CPU"

	depends on SYS_HAS_CPU_LOONGSON64

	select ARCH_HAS_PHYS_TO_DMA

	select CPU_SUPPORTS_64BIT_KERNEL
@@ -1448,17 +1452,20 @@ config CPU_LOONGSON64 
	select GPIOLIB

	select SWIOTLB

	help

		The Loongson GSx64 series of processor cores implements the

		MIPS64R2 instruction set with many extensions.

		The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor

		cores implements the MIPS64R2 instruction set with many extensions,

		including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,

		3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old

		Loongson-2E/2F is not covered here and will be removed in future.



config LOONGSON64_ENHANCEMENT

	bool "New Loongson GSx64E CPU Enhancements"

config LOONGSON3_ENHANCEMENT

	bool "New Loongson-3 CPU Enhancements"

	default n

	select CPU_MIPSR2

	select CPU_HAS_PREFETCH

	depends on CPU_LOONGSON64

	help

	  New Loongson GSx64E cores (since Loongson-3A R2, as opposed to Loongson-3A

	  New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A

	  R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as

	  FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User

	  Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
@@ -1467,17 +1474,17 @@ config LOONGSON64_ENHANCEMENT 
	  This option enable those enhancements which are not probed at run

	  time. If you want a generic kernel to run on all Loongson 3 machines,

	  please say 'N' here. If you want a high-performance kernel to run on

	  new Loongson 3 machines only, please say 'Y' here.

	  new Loongson-3 machines only, please say 'Y' here.



config CPU_LOONGSON3_WORKAROUNDS

	bool "Old Loongson 3 LLSC Workarounds"

	bool "Old Loongson-3 LLSC Workarounds"

	default y if SMP

	depends on CPU_LOONGSON64

	help

	  Loongson 3 processors have the llsc issues which require workarounds.

	  Loongson-3 processors have the llsc issues which require workarounds.

	  Without workarounds the system may hang unexpectedly.



	  Newer Loongson 3 will fix these issues and no workarounds are needed.

	  Newer Loongson-3 will fix these issues and no workarounds are needed.

	  The workarounds have no significant side effect on them but may

	  decrease the performance of the system so this option should be

	  disabled unless the kernel is intended to be run on old systems.

arch/mips/include/asm/hazards.h

+2 −2
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
 * TLB hazards

 */

#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \

	!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON64_ENHANCEMENT)

	!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT)



/*

 * MIPSR2 defines ehb for hazard avoidance
@@ -158,7 +158,7 @@ do { \ 
} while (0)



#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \

	defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON64_ENHANCEMENT) || \

	defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \

	defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)



/*

arch/mips/loongson64/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ if MACH_LOONGSON64 


config RS780_HPET

	bool "RS780/SBX00 HPET Timer"

	depends on CONFIG_MACH_LOONGSON64

	depends on MACH_LOONGSON64

	select MIPS_EXTERNAL_TIMER

	help

	  This option enables the hpet timer of AMD RS780/SBX00.

CRA Git | Maintained and supported by SUSTech CRA and CCSE