Commit cadfad87 authored by Andy Lutomirski's avatar Andy Lutomirski Committed by Thomas Gleixner
Browse files

x86/ioperm: Fix io bitmap invalidation on Xen PV 



tss_invalidate_io_bitmap() wasn't wired up properly through the pvop
machinery, so the TSS and Xen's io bitmap would get out of sync
whenever disabling a valid io bitmap.

Add a new pvop for tss_invalidate_io_bitmap() to fix it.

This is XSA-329.

Fixes: 22fe5b04 ("x86/ioperm: Move TSS bitmap update to exit to user work")
Signed-off-by: default avatarAndy Lutomirski <luto@kernel.org>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarJuergen Gross <jgross@suse.com>
Reviewed-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/d53075590e1f91c19f8af705059d3ff99424c020.1595030016.git.luto@kernel.org
parent 81e96851

arch/x86/include/asm/io_bitmap.h

+16 −0
Original line number Diff line number Diff line
@@ -19,12 +19,28 @@ struct task_struct; 
void io_bitmap_share(struct task_struct *tsk);

void io_bitmap_exit(struct task_struct *tsk);



static inline void native_tss_invalidate_io_bitmap(void)

{

	/*

	 * Invalidate the I/O bitmap by moving io_bitmap_base outside the

	 * TSS limit so any subsequent I/O access from user space will

	 * trigger a #GP.

	 *

	 * This is correct even when VMEXIT rewrites the TSS limit

	 * to 0x67 as the only requirement is that the base points

	 * outside the limit.

	 */

	this_cpu_write(cpu_tss_rw.x86_tss.io_bitmap_base,

		       IO_BITMAP_OFFSET_INVALID);

}



void native_tss_update_io_bitmap(void);



#ifdef CONFIG_PARAVIRT_XXL

#include <asm/paravirt.h>

#else

#define tss_update_io_bitmap native_tss_update_io_bitmap

#define tss_invalidate_io_bitmap native_tss_invalidate_io_bitmap

#endif



#else

arch/x86/include/asm/paravirt.h

+5 −0
Original line number Diff line number Diff line
@@ -302,6 +302,11 @@ static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g) 
}



#ifdef CONFIG_X86_IOPL_IOPERM

static inline void tss_invalidate_io_bitmap(void)

{

	PVOP_VCALL0(cpu.invalidate_io_bitmap);

}



static inline void tss_update_io_bitmap(void)

{

	PVOP_VCALL0(cpu.update_io_bitmap);

arch/x86/include/asm/paravirt_types.h

+1 −0
Original line number Diff line number Diff line
@@ -141,6 +141,7 @@ struct pv_cpu_ops { 
	void (*load_sp0)(unsigned long sp0);



#ifdef CONFIG_X86_IOPL_IOPERM

	void (*invalidate_io_bitmap)(void);

	void (*update_io_bitmap)(void);

#endif

arch/x86/kernel/paravirt.c

+2 −1
Original line number Diff line number Diff line
@@ -324,6 +324,7 @@ struct paravirt_patch_template pv_ops = { 
	.cpu.swapgs		= native_swapgs,



#ifdef CONFIG_X86_IOPL_IOPERM

	.cpu.invalidate_io_bitmap	= native_tss_invalidate_io_bitmap,

	.cpu.update_io_bitmap		= native_tss_update_io_bitmap,

#endif

arch/x86/kernel/process.c

+2 −16
Original line number Diff line number Diff line
@@ -322,20 +322,6 @@ void arch_setup_new_exec(void) 
}



#ifdef CONFIG_X86_IOPL_IOPERM

static inline void tss_invalidate_io_bitmap(struct tss_struct *tss)

{

	/*

	 * Invalidate the I/O bitmap by moving io_bitmap_base outside the

	 * TSS limit so any subsequent I/O access from user space will

	 * trigger a #GP.

	 *

	 * This is correct even when VMEXIT rewrites the TSS limit

	 * to 0x67 as the only requirement is that the base points

	 * outside the limit.

	 */

	tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;

}



static inline void switch_to_bitmap(unsigned long tifp)

{

	/*
@@ -346,7 +332,7 @@ static inline void switch_to_bitmap(unsigned long tifp) 
	 * user mode.

	 */

	if (tifp & _TIF_IO_BITMAP)

		tss_invalidate_io_bitmap(this_cpu_ptr(&cpu_tss_rw));

		tss_invalidate_io_bitmap();

}



static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
@@ -380,7 +366,7 @@ void native_tss_update_io_bitmap(void) 
	u16 *base = &tss->x86_tss.io_bitmap_base;



	if (!test_thread_flag(TIF_IO_BITMAP)) {

		tss_invalidate_io_bitmap(tss);

		native_tss_invalidate_io_bitmap();

		return;

	}

CRA Git | Maintained and supported by SUSTech CRA and CCSE