Commit cadbfd01 authored by LEROY Christophe's avatar LEROY Christophe Committed by Scott Wood
Browse files

powerpc/8xx: use _PAGE_RO instead of _PAGE_RW 



On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent a7b9f671

arch/powerpc/include/asm/pgtable-ppc32.h

+5 −6
Original line number Diff line number Diff line
@@ -178,12 +178,11 @@ static inline unsigned long pte_update(pte_t *p, 
	andc	%1,%0,%5\n\

	or	%1,%1,%6\n\

	/* 0x200 == Extended encoding, bit 22 */ \

	/* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \

	rlwimi	%1,%1,32-2,0x200\n /* get _PAGE_USER */ \

	rlwinm	%3,%1,32-1,0x200\n /* get _PAGE_RW */ \

	or	%1,%3,%1\n\

	xori	%1,%1,0x200\n"

"	stwcx.	%1,0,%4\n\

	/* Bit 22 has to be 1 when _PAGE_USER is unset and _PAGE_RO is set */ \

	rlwimi	%1,%1,32-1,0x200\n /* get _PAGE_RO */ \

	rlwinm	%3,%1,32-2,0x200\n /* get _PAGE_USER */ \

	andc	%1,%1,%3\n\

	stwcx.	%1,0,%4\n\

	bne-	1b"

	: "=&r" (old), "=&r" (tmp), "=m" (*p), "=&r" (tmp2)

	: "r" (p), "r" (clr), "r" (set), "m" (*p)

arch/powerpc/include/asm/pte-8xx.h

+4 −5
Original line number Diff line number Diff line
@@ -46,9 +46,9 @@ 
 * require a TLB exception handler change.  It is assumed unused bits

 * are always zero.

 */

#define _PAGE_RW	0x0400	/* lsb PP bits, inverted in HW */

#define _PAGE_RO	0x0400	/* lsb PP bits */

#define _PAGE_USER	0x0800	/* msb PP bits */

/* set when neither _PAGE_USER nor _PAGE_RW are set */

/* set when _PAGE_USER is unset and _PAGE_RO is set */

#define _PAGE_KNLRO	0x0200



#define _PMD_PRESENT	0x0001
@@ -62,9 +62,8 @@ 
#define PTE_ATOMIC_UPDATES	1



/* We need to add _PAGE_SHARED to kernel pages */

#define _PAGE_KERNEL_RO	(_PAGE_SHARED | _PAGE_KNLRO)

#define _PAGE_KERNEL_ROX	(_PAGE_EXEC | _PAGE_KNLRO)

#define _PAGE_KERNEL_RW	(_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)

#define _PAGE_KERNEL_RO	(_PAGE_SHARED | _PAGE_RO | _PAGE_KNLRO)

#define _PAGE_KERNEL_ROX	(_PAGE_EXEC | _PAGE_RO | _PAGE_KNLRO)



#endif /* __KERNEL__ */

#endif /*  _ASM_POWERPC_PTE_8xx_H */

arch/powerpc/kernel/head_8xx.S

+0 −3
Original line number Diff line number Diff line
@@ -441,9 +441,6 @@ DataStoreTLBMiss: 
	and	r11, r11, r10

	rlwimi	r10, r11, 0, _PAGE_PRESENT

#endif

	/* invert RW */

	xori	r10, r10, _PAGE_RW



	/* The Linux PTE won't go exactly into the MMU TLB.

	 * Software indicator bits 22 and 28 must be clear.

	 * Software indicator bits 24, 25, 26, and 27 must be

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