drm/amd/display: limit display clock to 100MHz to avoid FIFO error (cab5dec4) · Commits · 戴 / test

[Why] when changing display clock, SMU need to use power up DFS and use DENTIST to ramp DFS DID to switch target frequency before switching back to bypass. [How] fixed the minimum display clock to 100MHz, it's W/A the same with PCO. Signed-off-by:

Yu-ting Shen <Yu-ting.Shen@amd.com> Reviewed-by:

Tony Cheng <Tony.Cheng@amd.com> Acked-by:

Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:

Harry Wentland <harry.wentland@amd.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -2786,6 +2786,9 @@ void dcn20_calculate_dlg_params(
		!= dm_dram_clock_change_unsupported;
		context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

		if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;

		/*
		* An artifact of dml pipe split/odm is that pipes get merged back together for
		* calculation. Therefore we need to only extract for first pipe in ascending index order

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -859,6 +859,7 @@ static const struct dc_debug_options debug_defaults_drv = {
		.timing_trace = false,
		.clock_trace = true,
		.disable_pplib_clock_request = true,
		.min_disp_clk_khz = 100000,
		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
		.force_single_disp_pipe_split = false,
		.disable_dcc = DCC_ENABLE,

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