Commit cab25bc7 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
Browse files

MIPS: Extend hardware table walking support to MIPS64 



Extend the existing support for Hardware Table Walking (HTW) to MIPS64
systems by supporting PMDs & setting the pointer size bit in PWSize,
then ceasing to blacklist HTW on MIPS64 systems.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11224/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ecafe3e9

arch/mips/kernel/cpu-probe.c

+1 −2
Original line number Diff line number Diff line
@@ -536,8 +536,7 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) 
		c->options |= MIPS_CPU_SEGMENTS;

	if (config3 & MIPS_CONF3_MSA)

		c->ases |= MIPS_ASE_MSA;

	/* Only tested on 32-bit cores */

	if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {

	if (config3 & MIPS_CONF3_PW) {

		c->htw_seq = 0;

		c->options |= MIPS_CPU_HTW;

	}

arch/mips/mm/tlbex.c

+7 −1
Original line number Diff line number Diff line
@@ -2284,6 +2284,10 @@ static void config_htw_params(void) 
	/* re-initialize the PTI field including the even/odd bit */

	pwfield &= ~MIPS_PWFIELD_PTI_MASK;

	pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;

	if (CONFIG_PGTABLE_LEVELS >= 3) {

		pwfield &= ~MIPS_PWFIELD_MDI_MASK;

		pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;

	}

	/* Set the PTEI right shift */

	ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;

	pwfield |= ptei;
@@ -2305,9 +2309,11 @@ static void config_htw_params(void) 


	pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;

	pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;

	if (CONFIG_PGTABLE_LEVELS >= 3)

		pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;



	/* If XPA has been enabled, PTEs are 64-bit in size. */

	if (read_c0_pagegrain() & PG_ELPA)

	if (config_enabled(CONFIG_64BITS) || (read_c0_pagegrain() & PG_ELPA))

		pwsize |= 1;



	write_c0_pwsize(pwsize);

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