Commit caa4868e authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Olof Johansson
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ARM: tegra: add support for tegra30 interrupts 



Tegra30 has 1 extra legacy interrupt controller. Use the GIC ITLinesNumber
field to determine how many interrupt controllers we have and initialize
appropriately. Also make room for the extra tegra30 interrupts by moving
the GPIO IRQ base. This shouldn't affect existing code as it determines the
correct IRQ number for GPIOs using TEGRA_GPIO_TO_IRQ().

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Tested-by: default avatarStephen Warren <swarren@nvidia.com>
Acked-by: default avatarColin Cross <ccross@android.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 62aa2b53

arch/arm/mach-tegra/include/mach/iomap.h

+3 −0
Original line number Diff line number Diff line
@@ -74,6 +74,9 @@ 
#define TEGRA_QUATERNARY_ICTLR_BASE	0x60004300

#define TEGRA_QUATERNARY_ICTLR_SIZE	SZ_64



#define TEGRA_QUINARY_ICTLR_BASE	0x60004400

#define TEGRA_QUINARY_ICTLR_SIZE	SZ_64



#define TEGRA_TMR1_BASE			0x60005000

#define TEGRA_TMR1_SIZE			SZ_8

arch/arm/mach-tegra/include/mach/irqs.h

+4 −3
Original line number Diff line number Diff line
@@ -165,11 +165,12 @@ 
#define INT_QUAD_RES_30			(INT_QUAD_BASE + 30)

#define INT_QUAD_RES_31			(INT_QUAD_BASE + 31)



#define INT_MAIN_NR			(INT_QUAD_BASE + 32 - INT_PRI_BASE)



/* Tegra30 has 5 banks of 32 IRQs */

#define INT_MAIN_NR			(32 * 5)

#define INT_GPIO_BASE			(INT_PRI_BASE + INT_MAIN_NR)



#define INT_GPIO_NR			(28 * 8)

/* Tegra30 has 8 banks of 32 GPIOs */

#define INT_GPIO_NR			(32 * 8)



#define TEGRA_NR_IRQS			(INT_GPIO_BASE + INT_GPIO_NR)

arch/arm/mach-tegra/irq.c

+16 −4
Original line number Diff line number Diff line
@@ -44,14 +44,16 @@ 
#define ICTLR_COP_IER_CLR	0x38

#define ICTLR_COP_IEP_CLASS	0x3c



#define NUM_ICTLRS 4

#define FIRST_LEGACY_IRQ 32



static int num_ictlrs;



static void __iomem *ictlr_reg_base[] = {

	IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),

	IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),

	IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),

	IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),

	IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),

};



static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
@@ -60,7 +62,7 @@ static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg) 
	u32 mask;



	BUG_ON(irq < FIRST_LEGACY_IRQ ||

		irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);

		irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32);



	base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];

	mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
@@ -113,8 +115,18 @@ static int tegra_retrigger(struct irq_data *d) 
void __init tegra_init_irq(void)

{

	int i;

	void __iomem *distbase;



	distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);

	num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f;



	if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) {

		WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.",

			num_ictlrs, ARRAY_SIZE(ictlr_reg_base));

		num_ictlrs = ARRAY_SIZE(ictlr_reg_base);

	}



	for (i = 0; i < NUM_ICTLRS; i++) {

	for (i = 0; i < num_ictlrs; i++) {

		void __iomem *ictlr = ictlr_reg_base[i];

		writel(~0, ictlr + ICTLR_CPU_IER_CLR);

		writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
@@ -131,6 +143,6 @@ void __init tegra_init_irq(void) 
	 * initialized elsewhere under DT.

	 */

	if (!of_have_populated_dt())

		gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),

		gic_init(0, 29, distbase,

			IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));

}

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