Commit ca9153a3 authored by Ilya Yanok's avatar Ilya Yanok Committed by Paul Mackerras
Browse files

powerpc/44x: Support 16K/64K base page sizes on 44x 



This adds support for 16k and 64k page sizes on PowerPC 44x processors.

The PGDIR table is much smaller than a page when using 16k or 64k
pages (512 and 32 bytes respectively) so we allocate the PGDIR with
kzalloc() instead of __get_free_pages().

One PTE table covers rather a large memory area when using 16k or 64k
pages (32MB or 512MB respectively), so we can easily put FIXMAP and
PKMAP in the area covered by one PTE table.

Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
Signed-off-by: default avatarVladimir Panfilov <pvr@emcraft.com>
Signed-off-by: default avatarIlya Yanok <yanok@emcraft.com>
Acked-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 6ca4f749

arch/powerpc/Kconfig

+44 −14
Original line number Diff line number Diff line
@@ -405,23 +405,53 @@ config PPC_HAS_HASH_64K 
	depends on PPC64

	default n



config PPC_64K_PAGES

	bool "64k page size"

	depends on PPC64

	select PPC_HAS_HASH_64K

choice

	prompt "Page size"

	default PPC_4K_PAGES

	help

	  This option changes the kernel logical page size to 64k. On machines

	  without processor support for 64k pages, the kernel will simulate

	  them by loading each individual 4k page on demand transparently,

	  while on hardware with such support, it will be used to map

	  normal application pages.

	  Select the kernel logical page size. Increasing the page size

	  will reduce software overhead at each page boundary, allow

	  hardware prefetch mechanisms to be more effective, and allow

	  larger dma transfers increasing IO efficiency and reducing

	  overhead. However the utilization of memory will increase.

	  For example, each cached file will using a multiple of the

	  page size to hold its contents and the difference between the

	  end of file and the end of page is wasted.



	  Some dedicated systems, such as software raid serving with

	  accelerated calculations, have shown significant increases.



	  If you configure a 64 bit kernel for 64k pages but the

	  processor does not support them, then the kernel will simulate

	  them with 4k pages, loading them on demand, but with the

	  reduced software overhead and larger internal fragmentation.

	  For the 32 bit kernel, a large page option will not be offered

	  unless it is supported by the configured processor.



	  If unsure, choose 4K_PAGES.



config PPC_4K_PAGES

	bool "4k page size"



config PPC_16K_PAGES

	bool "16k page size" if 44x



config PPC_64K_PAGES

	bool "64k page size" if 44x || PPC_STD_MMU_64

	select PPC_HAS_HASH_64K if PPC_STD_MMU_64



endchoice



config FORCE_MAX_ZONEORDER

	int "Maximum zone order"

	range 9 64 if PPC_64K_PAGES

	default "9" if PPC_64K_PAGES

	range 13 64 if PPC64 && !PPC_64K_PAGES

	default "13" if PPC64 && !PPC_64K_PAGES

	range 9 64 if PPC_STD_MMU_64 && PPC_64K_PAGES

	default "9" if PPC_STD_MMU_64 && PPC_64K_PAGES

	range 13 64 if PPC_STD_MMU_64 && !PPC_64K_PAGES

	default "13" if PPC_STD_MMU_64 && !PPC_64K_PAGES

	range 9 64 if PPC_STD_MMU_32 && PPC_16K_PAGES

	default "9" if PPC_STD_MMU_32 && PPC_16K_PAGES

	range 7 64 if PPC_STD_MMU_32 && PPC_64K_PAGES

	default "7" if PPC_STD_MMU_32 && PPC_64K_PAGES

	range 11 64

	default "11"

	help
@@ -441,7 +471,7 @@ config FORCE_MAX_ZONEORDER 


config PPC_SUBPAGE_PROT

	bool "Support setting protections for 4k subpages"

	depends on PPC_64K_PAGES

	depends on PPC_STD_MMU_64 && PPC_64K_PAGES

	help

	  This option adds support for a system call to allow user programs

	  to set access permissions (read/write, readonly, or no access)

arch/powerpc/include/asm/highmem.h

+17 −2
Original line number Diff line number Diff line
@@ -38,9 +38,24 @@ extern pte_t *pkmap_page_table; 
 * easily, subsequent pte tables have to be allocated in one physical

 * chunk of RAM.

 */

#define LAST_PKMAP 	(1 << PTE_SHIFT)

#define LAST_PKMAP_MASK (LAST_PKMAP-1)

/*

 * We use one full pte table with 4K pages. And with 16K/64K pages pte

 * table covers enough memory (32MB and 512MB resp.) that both FIXMAP

 * and PKMAP can be placed in single pte table. We use 1024 pages for

 * PKMAP in case of 16K/64K pages.

 */

#ifdef CONFIG_PPC_4K_PAGES

#define PKMAP_ORDER	PTE_SHIFT

#else

#define PKMAP_ORDER	10

#endif

#define LAST_PKMAP	(1 << PKMAP_ORDER)

#ifndef CONFIG_PPC_4K_PAGES

#define PKMAP_BASE	(FIXADDR_START - PAGE_SIZE*(LAST_PKMAP + 1))

#else

#define PKMAP_BASE	((FIXADDR_START - PAGE_SIZE*(LAST_PKMAP + 1)) & PMD_MASK)

#endif

#define LAST_PKMAP_MASK	(LAST_PKMAP-1)

#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)

#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))

arch/powerpc/include/asm/mmu-44x.h

+17 −0
Original line number Diff line number Diff line
@@ -4,6 +4,8 @@ 
 * PPC440 support

 */



#include <asm/page.h>



#define PPC44x_MMUCR_TID	0x000000ff

#define PPC44x_MMUCR_STS	0x00010000
@@ -74,4 +76,19 @@ typedef struct { 
/* Size of the TLBs used for pinning in lowmem */

#define PPC_PIN_SIZE	(1 << 28)	/* 256M */



#if (PAGE_SHIFT == 12)

#define PPC44x_TLBE_SIZE	PPC44x_TLB_4K

#elif (PAGE_SHIFT == 14)

#define PPC44x_TLBE_SIZE	PPC44x_TLB_16K

#elif (PAGE_SHIFT == 16)

#define PPC44x_TLBE_SIZE	PPC44x_TLB_64K

#else

#error "Unsupported PAGE_SIZE"

#endif



#define PPC44x_PGD_OFF_SHIFT	(32 - PGDIR_SHIFT + PGD_T_LOG2)

#define PPC44x_PGD_OFF_MASK_BIT	(PGDIR_SHIFT - PGD_T_LOG2)

#define PPC44x_PTE_ADD_SHIFT	(32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)

#define PPC44x_PTE_ADD_MASK_BIT	(32 - PTE_T_LOG2 - PTE_SHIFT)



#endif /* _ASM_POWERPC_MMU_44X_H_ */

arch/powerpc/include/asm/page.h

+8 −5
Original line number Diff line number Diff line
@@ -19,12 +19,15 @@ 
#include <asm/kdump.h>



/*

 * On PPC32 page size is 4K. For PPC64 we support either 4K or 64K software

 * On regular PPC32 page size is 4K (but we support 4K/16K/64K pages

 * on PPC44x). For PPC64 we support either 4K or 64K software

 * page size. When using 64K pages however, whether we are really supporting

 * 64K pages in HW or not is irrelevant to those definitions.

 */

#ifdef CONFIG_PPC_64K_PAGES

#if defined(CONFIG_PPC_64K_PAGES)

#define PAGE_SHIFT		16

#elif defined(CONFIG_PPC_16K_PAGES)

#define PAGE_SHIFT		14

#else

#define PAGE_SHIFT		12

#endif
@@ -151,7 +154,7 @@ typedef struct { pte_basic_t pte; } pte_t; 
/* 64k pages additionally define a bigger "real PTE" type that gathers

 * the "second half" part of the PTE for pseudo 64k pages

 */

#ifdef CONFIG_PPC_64K_PAGES

#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_STD_MMU_64)

typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;

#else

typedef struct { pte_t pte; } real_pte_t;
@@ -191,10 +194,10 @@ typedef pte_basic_t pte_t; 
#define pte_val(x)	(x)

#define __pte(x)	(x)



#ifdef CONFIG_PPC_64K_PAGES

#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_STD_MMU_64)

typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;

#else

typedef unsigned long real_pte_t;

typedef pte_t real_pte_t;

#endif

arch/powerpc/include/asm/page_32.h

+5 −2
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ 
#define PTE_FLAGS_OFFSET	0

#endif



#define PTE_SHIFT	(PAGE_SHIFT - PTE_T_LOG2)	/* full page */



#ifndef __ASSEMBLY__

/*

 * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
@@ -26,10 +28,8 @@ 
 */

#ifdef CONFIG_PTE_64BIT

typedef unsigned long long pte_basic_t;

#define PTE_SHIFT	(PAGE_SHIFT - 3)	/* 512 ptes per page */

#else

typedef unsigned long pte_basic_t;

#define PTE_SHIFT	(PAGE_SHIFT - 2)	/* 1024 ptes per page */

#endif



struct page;
@@ -39,6 +39,9 @@ extern void copy_page(void *to, void *from); 


#include <asm-generic/page.h>



#define PGD_T_LOG2	(__builtin_ffs(sizeof(pgd_t)) - 1)

#define PTE_T_LOG2	(__builtin_ffs(sizeof(pte_t)) - 1)



#endif /* __ASSEMBLY__ */



#endif /* _ASM_POWERPC_PAGE_32_H */

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