Merge branch 'clk-rk3368' into clk-next

* Rockchip RK3368 Clock and Reset Unit

The RK3368 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.

Required Properties:

- compatible: should be "rockchip,rk3368-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

- #reset-cells: should be 1.

Optional Properties:

- rockchip,grf: phandle to the syscon managing the "general register files"

  If missing, pll rates are not changeable, due to the missing pll lock status.

Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be

used in device tree sources. Similar macros exist for the reset sources in

these files.

External clocks:

There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "xin24m" - crystal input - required,

 - "xin32k" - rtc clock - optional,

 - "ext_i2s" - external I2S clock - optional,

 - "ext_gmac" - external GMAC clock - optional

 - "ext_hsadc" - external HSADC clock - optional,

 - "ext_isp" - external ISP clock - optional,

 - "ext_jtag" - external JTAG clock - optional

 - "ext_vip" - external VIP clock - optional,

 - "usbotg_out" - output clock of the pll in the otg phy

Example: Clock controller node:

	cru: clock-controller@ff760000 {

		compatible = "rockchip,rk3368-cru";

		reg = <0x0 0xff760000 0x0 0x1000>;

		rockchip,grf = <&grf>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

Example: UART controller node that consumes the clock generated by the clock

  controller:

	uart0: serial@10124000 {

		compatible = "snps,dw-apb-uart";

		reg = <0x10124000 0x400>;

		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <1>;

		clocks = <&cru SCLK_UART0>;

	};

obj-y	+= clk.o

obj-y	+= clk-pll.o

obj-y	+= clk-cpu.o

obj-y	+= clk-inverter.o

obj-y	+= clk-mmc-phase.o

obj-$(CONFIG_RESET_CONTROLLER)	+= softrst.o

obj-y	+= clk-rk3188.o

obj-y	+= clk-rk3288.o

obj-y	+= clk-rk3368.o

/*

 * Copyright 2015 Heiko Stuebner <heiko@sntech.de>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <linux/slab.h>

#include <linux/clk-provider.h>

#include <linux/io.h>

#include <linux/spinlock.h>

#include <linux/kernel.h>

#include "clk.h"

struct rockchip_inv_clock {

	struct clk_hw	hw;

	void __iomem	*reg;

	int		shift;

	int		flags;

	spinlock_t	*lock;

};

#define to_inv_clock(_hw) container_of(_hw, struct rockchip_inv_clock, hw)

#define INVERTER_MASK 0x1

static int rockchip_inv_get_phase(struct clk_hw *hw)

{

	struct rockchip_inv_clock *inv_clock = to_inv_clock(hw);

	u32 val;

	val = readl(inv_clock->reg) >> inv_clock->shift;

	val &= INVERTER_MASK;

	return val ? 180 : 0;

}

static int rockchip_inv_set_phase(struct clk_hw *hw, int degrees)

{

	struct rockchip_inv_clock *inv_clock = to_inv_clock(hw);

	u32 val;

	if (degrees % 180 == 0) {

		val = !!degrees;

	} else {

		pr_err("%s: unsupported phase %d for %s\n",

		       __func__, degrees, __clk_get_name(hw->clk));

		return -EINVAL;

	}

	if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) {

		writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift),

		       inv_clock->reg);

	} else {

		unsigned long flags;

		u32 reg;

		spin_lock_irqsave(inv_clock->lock, flags);

		reg = readl(inv_clock->reg);

		reg &= ~BIT(inv_clock->shift);

		reg |= val;

		writel(reg, inv_clock->reg);

		spin_unlock_irqrestore(inv_clock->lock, flags);

	}

	return 0;

}

static const struct clk_ops rockchip_inv_clk_ops = {

	.get_phase	= rockchip_inv_get_phase,

	.set_phase	= rockchip_inv_set_phase,

};

struct clk *rockchip_clk_register_inverter(const char *name,

				const char *const *parent_names, u8 num_parents,

				void __iomem *reg, int shift, int flags,

				spinlock_t *lock)

{

	struct clk_init_data init;

	struct rockchip_inv_clock *inv_clock;

	struct clk *clk;

	inv_clock = kmalloc(sizeof(*inv_clock), GFP_KERNEL);

	if (!inv_clock)

		return NULL;

	init.name = name;

	init.num_parents = num_parents;

	init.flags = CLK_SET_RATE_PARENT;

	init.parent_names = parent_names;

	init.ops = &rockchip_inv_clk_ops;

	inv_clock->hw.init = &init;

	inv_clock->reg = reg;

	inv_clock->shift = shift;

	inv_clock->flags = flags;

	inv_clock->lock = lock;

	clk = clk_register(NULL, &inv_clock->hw);

	if (IS_ERR(clk))

		goto err_free;

	return clk;

err_free:

	kfree(inv_clock);

	return NULL;

}

#include <linux/slab.h>

#include <linux/clk-provider.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include "clk.h"

struct rockchip_mmc_clock {

	if (!mmc_clock)

		return NULL;

	init.name = name;

	init.num_parents = num_parents;

	init.parent_names = parent_names;

	init.ops = &rockchip_mmc_clk_ops;

	mmc_clock->reg = reg;

	mmc_clock->shift = shift;

	if (name)

		init.name = name;

	clk = clk_register(NULL, &mmc_clock->hw);

	if (IS_ERR(clk))

		goto err_free;

#define MFLAGS CLK_MUX_HIWORD_MASK

#define DFLAGS CLK_DIVIDER_HIWORD_MASK

#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)

#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK

/* 2 ^ (val + 1) */

static struct clk_div_table div_core_peri_t[] = {

	GATE(0, "pclkin_cif0", "ext_cif0", 0,

			RK2928_CLKGATE_CON(3), 3, GFLAGS),

	INVERTER(0, "pclk_cif0", "pclkin_cif0",

			RK2928_CLKSEL_CON(30), 8, IFLAGS),

	/*

	 * the 480m are generated inside the usb block from these clocks,

	COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0,

			RK2928_CLKSEL_CON(23), 0,

			RK2928_CLKGATE_CON(2), 7, GFLAGS),

	MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,

	MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,

			RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),

	INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",

			RK2928_CLKSEL_CON(22), 7, IFLAGS),

	COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,

			RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,

	GATE(0, "pclkin_cif1", "ext_cif1", 0,

			RK2928_CLKGATE_CON(3), 4, GFLAGS),

	INVERTER(0, "pclk_cif1", "pclkin_cif1",

			RK2928_CLKSEL_CON(30), 12, IFLAGS),

	COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,

			RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,