Commit ca6ffc64 authored by Jerome Glisse's avatar Jerome Glisse Committed by Dave Airlie
Browse files

drm/radeon/kms: Convert RS400/RS480 to new init path & fix legacy VGA (V3) 



Also cleanup register specific to RS400/RS480. This patch also fix
legacy VGA register used to disable VGA access we were programming
wrong register. Now we should properly disable VGA on r100 up to
rs400 asics. Note that RS400/RS480 resume is broken, it hangs the
computer while reprogramming dynamic clock, doesn't work either
without that patch. We need to spend more time investigating this
issue. Version 2 of the patch remove dead code that was left
commented out in the previous version. Version 3 correct the
placement on IGP of the VRAM inside GPU address space to match the
stollen RAM placement of IGP.

Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent f0ed1f65

drivers/gpu/drm/radeon/r100.c

+11 −3
Original line number Diff line number Diff line
@@ -3100,7 +3100,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 
	WREG32(R_000740_CP_CSQ_CNTL, 0);



	/* Save few CRTC registers */

	save->GENMO_WT = RREG32(R_0003C0_GENMO_WT);

	save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);

	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);

	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);

	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
@@ -3110,7 +3110,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 
	}



	/* Disable VGA aperture access */

	WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT);

	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);

	/* Disable cursor, overlay, crtc */

	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));

	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
@@ -3142,10 +3142,18 @@ void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 
				rdev->mc.vram_location);

	}

	/* Restore CRTC registers */

	WREG32(R_0003C0_GENMO_WT, save->GENMO_WT);

	WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);

	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);

	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);

	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {

		WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);

	}

}



void r100_vga_render_disable(struct radeon_device *rdev)

{

    u32 tmp;



    tmp = RREG8(R_0003C2_GENMO_WT);

	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);

}

drivers/gpu/drm/radeon/r100d.h

+19 −19
Original line number Diff line number Diff line
@@ -403,25 +403,25 @@ 
#define   S_000360_CUR2_LOCK(x)                        (((x) & 0x1) << 31)

#define   G_000360_CUR2_LOCK(x)                        (((x) >> 31) & 0x1)

#define   C_000360_CUR2_LOCK                           0x7FFFFFFF

#define R_0003C0_GENMO_WT                            0x0003C0

#define   S_0003C0_GENMO_MONO_ADDRESS_B(x)             (((x) & 0x1) << 0)

#define   G_0003C0_GENMO_MONO_ADDRESS_B(x)             (((x) >> 0) & 0x1)

#define   C_0003C0_GENMO_MONO_ADDRESS_B                0xFFFFFFFE

#define   S_0003C0_VGA_RAM_EN(x)                       (((x) & 0x1) << 1)

#define   G_0003C0_VGA_RAM_EN(x)                       (((x) >> 1) & 0x1)

#define   C_0003C0_VGA_RAM_EN                          0xFFFFFFFD

#define   S_0003C0_VGA_CKSEL(x)                        (((x) & 0x3) << 2)

#define   G_0003C0_VGA_CKSEL(x)                        (((x) >> 2) & 0x3)

#define   C_0003C0_VGA_CKSEL                           0xFFFFFFF3

#define   S_0003C0_ODD_EVEN_MD_PGSEL(x)                (((x) & 0x1) << 5)

#define   G_0003C0_ODD_EVEN_MD_PGSEL(x)                (((x) >> 5) & 0x1)

#define   C_0003C0_ODD_EVEN_MD_PGSEL                   0xFFFFFFDF

#define   S_0003C0_VGA_HSYNC_POL(x)                    (((x) & 0x1) << 6)

#define   G_0003C0_VGA_HSYNC_POL(x)                    (((x) >> 6) & 0x1)

#define   C_0003C0_VGA_HSYNC_POL                       0xFFFFFFBF

#define   S_0003C0_VGA_VSYNC_POL(x)                    (((x) & 0x1) << 7)

#define   G_0003C0_VGA_VSYNC_POL(x)                    (((x) >> 7) & 0x1)

#define   C_0003C0_VGA_VSYNC_POL                       0xFFFFFF7F

#define R_0003C2_GENMO_WT                            0x0003C0

#define   S_0003C2_GENMO_MONO_ADDRESS_B(x)             (((x) & 0x1) << 0)

#define   G_0003C2_GENMO_MONO_ADDRESS_B(x)             (((x) >> 0) & 0x1)

#define   C_0003C2_GENMO_MONO_ADDRESS_B                0xFE

#define   S_0003C2_VGA_RAM_EN(x)                       (((x) & 0x1) << 1)

#define   G_0003C2_VGA_RAM_EN(x)                       (((x) >> 1) & 0x1)

#define   C_0003C2_VGA_RAM_EN                          0xFD

#define   S_0003C2_VGA_CKSEL(x)                        (((x) & 0x3) << 2)

#define   G_0003C2_VGA_CKSEL(x)                        (((x) >> 2) & 0x3)

#define   C_0003C2_VGA_CKSEL                           0xF3

#define   S_0003C2_ODD_EVEN_MD_PGSEL(x)                (((x) & 0x1) << 5)

#define   G_0003C2_ODD_EVEN_MD_PGSEL(x)                (((x) >> 5) & 0x1)

#define   C_0003C2_ODD_EVEN_MD_PGSEL                   0xDF

#define   S_0003C2_VGA_HSYNC_POL(x)                    (((x) & 0x1) << 6)

#define   G_0003C2_VGA_HSYNC_POL(x)                    (((x) >> 6) & 0x1)

#define   C_0003C2_VGA_HSYNC_POL                       0xBF

#define   S_0003C2_VGA_VSYNC_POL(x)                    (((x) & 0x1) << 7)

#define   G_0003C2_VGA_VSYNC_POL(x)                    (((x) >> 7) & 0x1)

#define   C_0003C2_VGA_VSYNC_POL                       0x7F

#define R_0003F8_CRTC2_GEN_CNTL                      0x0003F8

#define   S_0003F8_CRTC2_DBL_SCAN_EN(x)                (((x) & 0x1) << 0)

#define   G_0003F8_CRTC2_DBL_SCAN_EN(x)                (((x) >> 0) & 0x1)

drivers/gpu/drm/radeon/r300.c

+15 −1
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#include "radeon_drm.h"

#include "r100_track.h"

#include "r300d.h"

#include "rv350d.h"



#include "r300_reg_safe.h"
@@ -63,7 +64,6 @@ int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 
 * Some of these functions might be used by newer ASICs.

 */

void r300_gpu_init(struct radeon_device *rdev);

int r300_mc_wait_for_idle(struct radeon_device *rdev);

int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
@@ -1265,3 +1265,17 @@ void r300_mc_program(struct radeon_device *rdev) 
		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));

	r100_mc_resume(rdev, &save);

}



void r300_clock_startup(struct radeon_device *rdev)

{

	u32 tmp;



	if (radeon_dynclks != -1 && radeon_dynclks)

		radeon_legacy_set_clock_gating(rdev, 1);

	/* We need to force on some of the block */

	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);

	tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);

	if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))

		tmp |= S_00000D_FORCE_VAP(1);

	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);

}

drivers/gpu/drm/radeon/r300d.h

+92 −0
Original line number Diff line number Diff line
@@ -98,4 +98,96 @@ 
#define   C_000170_AGP_BASE_ADDR                       0x00000000





#define R_00000D_SCLK_CNTL                           0x00000D

#define   S_00000D_SCLK_SRC_SEL(x)                     (((x) & 0x7) << 0)

#define   G_00000D_SCLK_SRC_SEL(x)                     (((x) >> 0) & 0x7)

#define   C_00000D_SCLK_SRC_SEL                        0xFFFFFFF8

#define   S_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 3)

#define   G_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) >> 3) & 0x1)

#define   C_00000D_CP_MAX_DYN_STOP_LAT                 0xFFFFFFF7

#define   S_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 4)

#define   G_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) >> 4) & 0x1)

#define   C_00000D_HDP_MAX_DYN_STOP_LAT                0xFFFFFFEF

#define   S_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 5)

#define   G_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) >> 5) & 0x1)

#define   C_00000D_TV_MAX_DYN_STOP_LAT                 0xFFFFFFDF

#define   S_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 6)

#define   G_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) >> 6) & 0x1)

#define   C_00000D_E2_MAX_DYN_STOP_LAT                 0xFFFFFFBF

#define   S_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 7)

#define   G_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) >> 7) & 0x1)

#define   C_00000D_SE_MAX_DYN_STOP_LAT                 0xFFFFFF7F

#define   S_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) & 0x1) << 8)

#define   G_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) >> 8) & 0x1)

#define   C_00000D_IDCT_MAX_DYN_STOP_LAT               0xFFFFFEFF

#define   S_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 9)

#define   G_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) >> 9) & 0x1)

#define   C_00000D_VIP_MAX_DYN_STOP_LAT                0xFFFFFDFF

#define   S_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 10)

#define   G_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) >> 10) & 0x1)

#define   C_00000D_RE_MAX_DYN_STOP_LAT                 0xFFFFFBFF

#define   S_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 11)

#define   G_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) >> 11) & 0x1)

#define   C_00000D_PB_MAX_DYN_STOP_LAT                 0xFFFFF7FF

#define   S_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 12)

#define   G_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) >> 12) & 0x1)

#define   C_00000D_TAM_MAX_DYN_STOP_LAT                0xFFFFEFFF

#define   S_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 13)

#define   G_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) >> 13) & 0x1)

#define   C_00000D_TDM_MAX_DYN_STOP_LAT                0xFFFFDFFF

#define   S_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 14)

#define   G_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) >> 14) & 0x1)

#define   C_00000D_RB_MAX_DYN_STOP_LAT                 0xFFFFBFFF

#define   S_00000D_FORCE_DISP2(x)                      (((x) & 0x1) << 15)

#define   G_00000D_FORCE_DISP2(x)                      (((x) >> 15) & 0x1)

#define   C_00000D_FORCE_DISP2                         0xFFFF7FFF

#define   S_00000D_FORCE_CP(x)                         (((x) & 0x1) << 16)

#define   G_00000D_FORCE_CP(x)                         (((x) >> 16) & 0x1)

#define   C_00000D_FORCE_CP                            0xFFFEFFFF

#define   S_00000D_FORCE_HDP(x)                        (((x) & 0x1) << 17)

#define   G_00000D_FORCE_HDP(x)                        (((x) >> 17) & 0x1)

#define   C_00000D_FORCE_HDP                           0xFFFDFFFF

#define   S_00000D_FORCE_DISP1(x)                      (((x) & 0x1) << 18)

#define   G_00000D_FORCE_DISP1(x)                      (((x) >> 18) & 0x1)

#define   C_00000D_FORCE_DISP1                         0xFFFBFFFF

#define   S_00000D_FORCE_TOP(x)                        (((x) & 0x1) << 19)

#define   G_00000D_FORCE_TOP(x)                        (((x) >> 19) & 0x1)

#define   C_00000D_FORCE_TOP                           0xFFF7FFFF

#define   S_00000D_FORCE_E2(x)                         (((x) & 0x1) << 20)

#define   G_00000D_FORCE_E2(x)                         (((x) >> 20) & 0x1)

#define   C_00000D_FORCE_E2                            0xFFEFFFFF

#define   S_00000D_FORCE_SE(x)                         (((x) & 0x1) << 21)

#define   G_00000D_FORCE_SE(x)                         (((x) >> 21) & 0x1)

#define   C_00000D_FORCE_SE                            0xFFDFFFFF

#define   S_00000D_FORCE_IDCT(x)                       (((x) & 0x1) << 22)

#define   G_00000D_FORCE_IDCT(x)                       (((x) >> 22) & 0x1)

#define   C_00000D_FORCE_IDCT                          0xFFBFFFFF

#define   S_00000D_FORCE_VIP(x)                        (((x) & 0x1) << 23)

#define   G_00000D_FORCE_VIP(x)                        (((x) >> 23) & 0x1)

#define   C_00000D_FORCE_VIP                           0xFF7FFFFF

#define   S_00000D_FORCE_RE(x)                         (((x) & 0x1) << 24)

#define   G_00000D_FORCE_RE(x)                         (((x) >> 24) & 0x1)

#define   C_00000D_FORCE_RE                            0xFEFFFFFF

#define   S_00000D_FORCE_PB(x)                         (((x) & 0x1) << 25)

#define   G_00000D_FORCE_PB(x)                         (((x) >> 25) & 0x1)

#define   C_00000D_FORCE_PB                            0xFDFFFFFF

#define   S_00000D_FORCE_TAM(x)                        (((x) & 0x1) << 26)

#define   G_00000D_FORCE_TAM(x)                        (((x) >> 26) & 0x1)

#define   C_00000D_FORCE_TAM                           0xFBFFFFFF

#define   S_00000D_FORCE_TDM(x)                        (((x) & 0x1) << 27)

#define   G_00000D_FORCE_TDM(x)                        (((x) >> 27) & 0x1)

#define   C_00000D_FORCE_TDM                           0xF7FFFFFF

#define   S_00000D_FORCE_RB(x)                         (((x) & 0x1) << 28)

#define   G_00000D_FORCE_RB(x)                         (((x) >> 28) & 0x1)

#define   C_00000D_FORCE_RB                            0xEFFFFFFF

#define   S_00000D_FORCE_TV_SCLK(x)                    (((x) & 0x1) << 29)

#define   G_00000D_FORCE_TV_SCLK(x)                    (((x) >> 29) & 0x1)

#define   C_00000D_FORCE_TV_SCLK                       0xDFFFFFFF

#define   S_00000D_FORCE_SUBPIC(x)                     (((x) & 0x1) << 30)

#define   G_00000D_FORCE_SUBPIC(x)                     (((x) >> 30) & 0x1)

#define   C_00000D_FORCE_SUBPIC                        0xBFFFFFFF

#define   S_00000D_FORCE_OV0(x)                        (((x) & 0x1) << 31)

#define   G_00000D_FORCE_OV0(x)                        (((x) >> 31) & 0x1)

#define   C_00000D_FORCE_OV0                           0x7FFFFFFF



#endif

drivers/gpu/drm/radeon/r420.c

+5 −0
Original line number Diff line number Diff line
@@ -155,6 +155,9 @@ static void r420_debugfs(struct radeon_device *rdev) 
static void r420_clock_resume(struct radeon_device *rdev)

{

	u32 sclk_cntl;



	if (radeon_dynclks != -1 && radeon_dynclks)

		radeon_atom_set_clock_gating(rdev, 1);

	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);

	sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);

	if (rdev->family == CHIP_R420)
@@ -167,6 +170,8 @@ static int r420_startup(struct radeon_device *rdev) 
	int r;



	r300_mc_program(rdev);

	/* Resume clock */

	r420_clock_resume(rdev);

	/* Initialize GART (initialize after TTM so we can allocate

	 * memory through TTM but finalize after TTM) */

	if (rdev->flags & RADEON_IS_PCIE) {

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