Commit ca52a47a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v5.10-rockchip-clk1' of... 

Merge tag 'v5.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

Ability to build the clock driver as module and removal
of an unused parent-names struct.

* tag 'v5.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rk3399: Support module build
  clk: rockchip: fix the clk config to support module build
  clk: rockchip: Export some clock common APIs for module drivers
  clk: rockchip: Export rockchip_register_softrst()
  clk: rockchip: Export rockchip_clk_register_ddrclk()
  clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
  clk: rockchip: rk3308: drop unused mux_timer_src_p
parents 9123e3a7 70d839e2

drivers/clk/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig" 
source "drivers/clk/mvebu/Kconfig"

source "drivers/clk/qcom/Kconfig"

source "drivers/clk/renesas/Kconfig"

source "drivers/clk/rockchip/Kconfig"

source "drivers/clk/samsung/Kconfig"

source "drivers/clk/sifive/Kconfig"

source "drivers/clk/sprd/Kconfig"

drivers/clk/rockchip/Kconfig

0 → 100644
+78 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

# common clock support for ROCKCHIP SoC family.



config COMMON_CLK_ROCKCHIP

	bool "Rockchip clock controller common support"

	depends on ARCH_ROCKCHIP

	default ARCH_ROCKCHIP

	help

	  Say y here to enable common clock controller for Rockchip platforms.



if COMMON_CLK_ROCKCHIP

config CLK_PX30

	bool "Rockchip PX30 clock controller support"

	default y

	help

	  Build the driver for PX30 Clock Driver.



config CLK_RV110X

	bool "Rockchip RV110x clock controller support"

	default y

	help

	  Build the driver for RV110x Clock Driver.



config CLK_RK3036

	bool "Rockchip RK3036 clock controller support"

	default y

	help

	  Build the driver for RK3036 Clock Driver.



config CLK_RK312X

	bool "Rockchip RK312x clock controller support"

	default y

	help

	  Build the driver for RK312x Clock Driver.



config CLK_RK3188

	bool "Rockchip RK3188 clock controller support"

	default y

	help

	  Build the driver for RK3188 Clock Driver.



config CLK_RK322X

	bool "Rockchip RK322x clock controller support"

	default y

	help

	  Build the driver for RK322x Clock Driver.



config CLK_RK3288

	bool "Rockchip RK3288 clock controller support"

	depends on ARM

	default y

	help

	  Build the driver for RK3288 Clock Driver.



config CLK_RK3308

	bool "Rockchip RK3308 clock controller support"

	default y

	help

	  Build the driver for RK3308 Clock Driver.



config CLK_RK3328

	bool "Rockchip RK3328 clock controller support"

	default y

	help

	  Build the driver for RK3328 Clock Driver.



config CLK_RK3368

	bool "Rockchip RK3368 clock controller support"

	default y

	help

	  Build the driver for RK3368 Clock Driver.



config CLK_RK3399

	tristate "Rockchip RK3399 clock controller support"

	default y

	help

	  Build the driver for RK3399 Clock Driver.

endif

drivers/clk/rockchip/Makefile

+22 −20
Original line number Diff line number Diff line
@@ -3,24 +3,26 @@ 
# Rockchip Clock specific Makefile

#



obj-y	+= clk.o

obj-y	+= clk-pll.o

obj-y	+= clk-cpu.o

obj-y	+= clk-half-divider.o

obj-y	+= clk-inverter.o

obj-y	+= clk-mmc-phase.o

obj-y	+= clk-muxgrf.o

obj-y	+= clk-ddr.o

obj-$(CONFIG_RESET_CONTROLLER)	+= softrst.o

obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o



obj-y	+= clk-px30.o

obj-y	+= clk-rv1108.o

obj-y	+= clk-rk3036.o

obj-y	+= clk-rk3128.o

obj-y	+= clk-rk3188.o

obj-y	+= clk-rk3228.o

obj-y	+= clk-rk3288.o

obj-y	+= clk-rk3308.o

obj-y	+= clk-rk3328.o

obj-y	+= clk-rk3368.o

obj-y	+= clk-rk3399.o
 
clk-rockchip-y += clk.o

clk-rockchip-y += clk-pll.o

clk-rockchip-y += clk-cpu.o

clk-rockchip-y += clk-half-divider.o

clk-rockchip-y += clk-inverter.o

clk-rockchip-y += clk-mmc-phase.o

clk-rockchip-y += clk-muxgrf.o

clk-rockchip-y += clk-ddr.o

clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o



obj-$(CONFIG_CLK_PX30)          += clk-px30.o

obj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o

obj-$(CONFIG_CLK_RK3036)        += clk-rk3036.o

obj-$(CONFIG_CLK_RK312X)        += clk-rk3128.o

obj-$(CONFIG_CLK_RK3188)        += clk-rk3188.o

obj-$(CONFIG_CLK_RK322X)        += clk-rk3228.o

obj-$(CONFIG_CLK_RK3288)        += clk-rk3288.o

obj-$(CONFIG_CLK_RK3308)        += clk-rk3308.o

obj-$(CONFIG_CLK_RK3328)        += clk-rk3328.o

obj-$(CONFIG_CLK_RK3368)        += clk-rk3368.o

obj-$(CONFIG_CLK_RK3399)        += clk-rk3399.o

drivers/clk/rockchip/clk-ddr.c

+1 −0
Original line number Diff line number Diff line
@@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, 


	return clk;

}

EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk);

drivers/clk/rockchip/clk-half-divider.c

+10 −8
Original line number Diff line number Diff line
@@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, 
					  unsigned long flags,

					  spinlock_t *lock)

{

	struct clk *clk;

	struct clk_hw *hw;

	struct clk_mux *mux = NULL;

	struct clk_gate *gate = NULL;

	struct clk_divider *div = NULL;
@@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, 
		div_ops = &clk_half_divider_ops;

	}



	clk = clk_register_composite(NULL, name, parent_names, num_parents,

	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,

				       mux ? &mux->hw : NULL, mux_ops,

				       div ? &div->hw : NULL, div_ops,

				       gate ? &gate->hw : NULL, gate_ops,

				       flags);

	if (IS_ERR(hw))

		goto err_div;



	return clk;

	return hw->clk;

err_div:

	kfree(gate);

err_gate:

	kfree(mux);

	return ERR_PTR(-ENOMEM);

	return ERR_CAST(hw);

}

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