drm/bridge: tc358767: cleanup aux_link_setup (ca342386) · Commits · 戴 / test

The driver sets up AUX link at probe time, but, for some reason, also sets the main link's number of lanes using tc->link.base.num_lanes. This is not needed nor correct, as the number of lanes has not been decided yet. The number of lanes will be set later during main link setup. Modify aux_link_setup so that it does not use tc->link, and thus makes aux setup independent of the link probing. Signed-off-by:

Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by:

Andrzej Hajda <a.hajda@samsung.com> Reviewed-by:

Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:

Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528082747.3631-7-tomi.valkeinen@ti.com

drivers/gpu/drm/bridge/tc358767.c

+3 −6

Original line number	Diff line number	Diff line
		@@ -542,7 +542,6 @@ static int tc_aux_link_setup(struct tc_data *tc)
		unsigned long rate;
		u32 value;
		int ret;
		u32 dp_phy_ctrl;

		rate = clk_get_rate(tc->refclk);
		switch (rate) {
		@@ -567,10 +566,7 @@ static int tc_aux_link_setup(struct tc_data *tc)
		value \|= SYSCLK_SEL_LSCLK \| LSCLK_DIV_2;
		tc_write(SYS_PLLPARAM, value);

		dp_phy_ctrl = BGREN \| PWR_SW_EN \| PHY_A0_EN;
		if (tc->link.base.num_lanes == 2)
		dp_phy_ctrl \|= PHY_2LANE;
		tc_write(DP_PHY_CTRL, dp_phy_ctrl);
		tc_write(DP_PHY_CTRL, BGREN \| PWR_SW_EN \| PHY_A0_EN);

		/*
		* Initially PLLs are in bypass. Force PLL parameter update,
		@@ -587,8 +583,9 @@ static int tc_aux_link_setup(struct tc_data *tc)
		if (ret == -ETIMEDOUT) {
		dev_err(tc->dev, "Timeout waiting for PHY to become ready");
		return ret;
		} else if (ret)
		} else if (ret) {
		goto err;
		}

		/* Setup AUX link */
		tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN \|

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