Commit ca2618b5 authored Apr 27, 2018 by Kishon Vijay Abraham I Committed by Tony Lindgren May 03, 2018

ARM: dts: dra7-mmc-iodelay: Add a new pinctrl group for clk line without pullup



During a short period when the bus voltage is switched from 3.3v to 1.8v,
(to enumerate UHS mode), the mmc module is disabled and the mmc IO lines
are kept in a state according to the programmed pad mux pull type.

According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications
Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the
host should hold CLK low for at least 5ms.

In order to keep the card line low during voltage switch, the pad mux of
mmc1_clk line should be configured to pull down.

Add a new pinctrl group for clock line without pullup to be used in boards
where mmc1_clk line is not connected to an external pullup.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

parent bcf3c113

arch/arm/boot/dts/dra7-mmc-iodelay.dtsi

0 → 100644

+19 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0
		/*
		* MMC IOdelay values for TI's DRA7xx SoCs.
		* Copyright (C) 2018 Texas Instruments
		* Author: Kishon Vijay Abraham I <kishon@ti.com>
		*/

		&dra7_pmx_core {
		mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu {
		pinctrl-single,pins = <
		DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* mmc1_clk.clk */
		DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_cmd.cmd */
		DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat0.dat0 */
		DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat1.dat1 */
		DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat2.dat2 */
		DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
		};
		};

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