Commit ca1b4974 authored by Hans de Goede's avatar Hans de Goede Committed by Tejun Heo
Browse files

ahci: Annotate PCI ids for mobile Intel chipsets as such 



Intel uses different SATA PCI ids for the Desktop and Mobile SKUs of their
chipsets. For older models the comment describing which chipset the PCI id
is for, aksi indicates when we're dealing with a mobile SKU. Extend the
comments for recent chipsets to also indicate mobile SKUs.

The information this commit adds comes from Intel's chipset datasheets.

This commit is a preparation patch for allowing a different default
sata link powermanagement policy for mobile chipsets.

Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarTejun Heo <tj@kernel.org>
parent 2dc0b46b

drivers/ata/ahci.c

+16 −16
Original line number Diff line number Diff line
@@ -268,9 +268,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */

	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */

	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */

	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */

	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH M AHCI */

	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */

	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */

	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH M RAID */

	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */

	{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */

	{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
@@ -293,9 +293,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */

	{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */

	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */

	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */

	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT M AHCI */

	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */

	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */

	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT M RAID */

	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */

	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */

	{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
@@ -304,20 +304,20 @@ static const struct pci_device_id ahci_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */

	{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */

	{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */

	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */

	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point M AHCI */

	{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */

	{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */

	{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */

	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */

	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point M RAID */

	{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point M AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point M RAID */

	{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point M RAID */

	{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point M RAID */

	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */

	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */

	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
@@ -358,21 +358,21 @@ static const struct pci_device_id ahci_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series M AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series M RAID */

	{ PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series M RAID */

	{ PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series M RAID */

	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */

	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */

	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */

	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H M AHCI */

	{ PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */

	{ PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */

	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */

	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H M RAID */

	{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */

	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/

	{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/

CRA Git | Maintained and supported by SUSTech CRA and CCSE