Commit c9f3f081 authored by Rahul Sharma's avatar Rahul Sharma Committed by Mike Turquette
Browse files

clk/exynos5420: add sclk_hdmiphy to the list of special clocks



Add sclk_hdmiphy to the list of exposed clocks. This is required
by hdmi driver to change the parent of hdmi clock.

Signed-off-by: default avatarRahul Sharma <rahul.sharma@samsung.com>
Acked-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent a5828a6c
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+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ clock which they consume.
  sclk_pwm		155
  sclk_gscl_wa		156
  sclk_gscl_wb		157
  sclk_hdmiphy		158

   [Peripheral Clock Gates]

+2 −2
Original line number Diff line number Diff line
@@ -120,7 +120,7 @@ enum exynos5420_clks {
	sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
	sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
	sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
	sclk_pwm, sclk_gscl_wa, sclk_gscl_wb,
	sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,

	/* gate clocks */
	aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
@@ -297,7 +297,7 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initda

/* fixed rate clocks generated inside the soc */
static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
	FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
	FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
	FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
	FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
	FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),