Commit c9e28c25 authored by Sowjanya Komatineni's avatar Sowjanya Komatineni Committed by Thierry Reding
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clk: tegra: Remove CLK_M_DIV fixed clocks 



Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has
OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are the possible
parents of PMC clocks for Tegra30 through Tegra210.

Tegra PMC clock parents are changed to use OSC_DIV clocks.

So, this patch removes CLK_M_DIV fixed clocks

Tested-by: default avatarDmitry Osipenko <digetx@gmail.com>
Reviewed-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 6fe38aa8

drivers/clk/tegra/clk-id.h

+0 −2
Original line number Diff line number Diff line
@@ -44,8 +44,6 @@ enum clk_id { 
	tegra_clk_clk72Mhz,

	tegra_clk_clk72Mhz_8,

	tegra_clk_clk_m,

	tegra_clk_clk_m_div2,

	tegra_clk_clk_m_div4,

	tegra_clk_osc,

	tegra_clk_osc_div2,

	tegra_clk_osc_div4,

drivers/clk/tegra/clk-tegra-fixed.c

+0 −16
Original line number Diff line number Diff line
@@ -105,22 +105,6 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks) 
		clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);

		*dt_clk = clk;

	}



	/* clk_m_div2 */

	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);

	if (dt_clk) {

		clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",

					CLK_SET_RATE_PARENT, 1, 2);

		*dt_clk = clk;

	}



	/* clk_m_div4 */

	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);

	if (dt_clk) {

		clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",

					CLK_SET_RATE_PARENT, 1, 4);

		*dt_clk = clk;

	}

}



void tegra_clk_osc_resume(void __iomem *clk_base)

drivers/clk/tegra/clk-tegra114.c

+0 −15
Original line number Diff line number Diff line
@@ -735,8 +735,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },

	[tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },

	[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },

	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },

	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },

	[tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },

	[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },

	[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
@@ -818,8 +816,6 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },

	{ .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },

	{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },

	{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },

	{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },

	{ .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },

	{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },

	{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
@@ -906,17 +902,6 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base) 
	/* clk_32k */

	clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);

	clks[TEGRA114_CLK_CLK_32K] = clk;



	/* clk_m_div2 */

	clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",

					CLK_SET_RATE_PARENT, 1, 2);

	clks[TEGRA114_CLK_CLK_M_DIV2] = clk;



	/* clk_m_div4 */

	clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",

					CLK_SET_RATE_PARENT, 1, 4);

	clks[TEGRA114_CLK_CLK_M_DIV4] = clk;



}



static void __init tegra114_pll_init(void __iomem *clk_base,

drivers/clk/tegra/clk-tegra124.c

+0 −4
Original line number Diff line number Diff line
@@ -860,8 +860,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },

	[tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },

	[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },

	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },

	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },

	[tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },

	[tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },

	[tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
@@ -944,8 +942,6 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },

	{ .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },

	{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },

	{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },

	{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },

	{ .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },

	{ .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },

	{ .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },

drivers/clk/tegra/clk-tegra210.c

+0 −4
Original line number Diff line number Diff line
@@ -2371,8 +2371,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },

	[tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },

	[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },

	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },

	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },

	[tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },

	[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },

	[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
@@ -2500,8 +2498,6 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },

	{ .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },

	{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },

	{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },

	{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },

	{ .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },

	{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },

	{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },

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