[PATCH] i386: use set_pte macros in a couple places where they were missing (c9b02a24) · Commits · 戴 / test

Also, setting PDPEs in PAE mode does not require atomic operations, since the PDPEs are cached by the processor, and only reloaded on an explicit or implicit reload of CR3. Since the four PDPEs must always be present in an active root, and the kernel PDPE is never updated, we are safe even from SMIs and interrupts / NMIs using task gates (which reload CR3). Actually, much of this is moot, since the user PDPEs are never updated either, and the only usage of task gates is by the doublefault handler. It appears the only place PGDs get updated in PAE mode is in init_low_mappings() / zap_low_mapping() for initial page table creation and recovery from ACPI sleep state, and these sites are safe by inspection. Getting rid of the cmpxchg8b saves code space and 720 cycles in pgd_alloc on P4. Signed-off-by:

Zachary Amsden <zach@vmware.com> Signed-off-by:

Andrew Morton <akpm@osdl.org> Signed-off-by:

Linus Torvalds <torvalds@osdl.org>

arch/i386/mm/init.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -349,7 +349,7 @@ static void __init pagetable_init (void)
		* All user-space mappings are explicitly cleared after
		* SMP startup.
		*/
		pgd_base[0] = pgd_base[USER_PTRS_PER_PGD];
		set_pgd(&pgd_base[0], pgd_base[USER_PTRS_PER_PGD]);
		#endif
		}

arch/i386/mm/pageattr.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -12,6 +12,7 @@
		#include <asm/uaccess.h>
		#include <asm/processor.h>
		#include <asm/tlbflush.h>
		#include <asm/pgalloc.h>

		static DEFINE_SPINLOCK(cpa_lock);
		static struct list_head df_list = LIST_HEAD_INIT(df_list);
		@@ -52,8 +53,8 @@ static struct page *split_large_page(unsigned long address, pgprot_t prot)
		addr = address & LARGE_PAGE_MASK;
		pbase = (pte_t *)page_address(base);
		for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE) {
		pbase[i] = pfn_pte(addr >> PAGE_SHIFT,
		addr == address ? prot : PAGE_KERNEL);
		set_pte(&pbase[i], pfn_pte(addr >> PAGE_SHIFT,
		addr == address ? prot : PAGE_KERNEL));
		}
		return base;
		}

include/asm-i386/pgtable-3level.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -64,7 +64,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
		#define set_pmd(pmdptr,pmdval) \
		set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval))
		#define set_pud(pudptr,pudval) \
		set_64bit((unsigned long long *)(pudptr),pud_val(pudval))
		(*(pudptr) = (pudval))

		/*
		* Pentium-II erratum A13: in PAE mode we explicitly have to flush

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