drm/i915: enable PCH PLL, FDI training and transcoder even for eDP (c98e9dcf) · Commits · 戴 / test

eDP panels require these to be set up prior to panel power sequencing, or they'll fail to power on due to an "asset not ready" check. And of course, eDP panels attached to anything other than DP_A need them enabled regardless, since they'll be driven from the CPU through FDI out to the PCH. Signed-off-by:

Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:

Chris Wilson <chris@chris-wilson.co.uk>

drivers/gpu/drm/i915/intel_display.c

+119 −123

Original line number	Diff line number	Diff line
		@@ -1889,7 +1889,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
		}
		}

		if (!HAS_eDP) {
		/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		temp = I915_READ(fdi_rx_reg);
		/*
		@@ -1917,7 +1916,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
		I915_READ(fdi_tx_reg);
		udelay(100);
		}
		}

		/* Enable panel fitting for LVDS */
		if (dev_priv->pch_pf_size &&
		@@ -1951,7 +1949,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
		I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
		}

		if (!HAS_eDP) {
		/* For PCH output, training FDI link */
		if (IS_GEN6(dev))
		gen6_fdi_link_train(crtc);
		@@ -2058,7 +2055,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)

		if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100))
		DRM_ERROR("failed to enable transcoder\n");
		}

		intel_crtc_load_lut(crtc);

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