Commit c9833044 authored by Anson Huang's avatar Anson Huang Committed by Viresh Kumar
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cpufreq: imx-cpufreq-dt: Correct i.MX8MP's market segment fuse location 



i.MX8MP's market segment fuse field is bit[6:5], correct it.

Fixes: 83fe39ad ("cpufreq: imx-cpufreq-dt: Add i.MX8MP support")
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent 4bd8459b

drivers/cpufreq/imx-cpufreq-dt.c

+9 −1
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ 
#define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK	(0xf << 8)

#define OCOTP_CFG3_MKT_SEGMENT_SHIFT    6

#define OCOTP_CFG3_MKT_SEGMENT_MASK     (0x3 << 6)

#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT    5

#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK     (0x3 << 5)



/* cpufreq-dt device registered by imx-cpufreq-dt */

static struct platform_device *cpufreq_dt_pdev;
@@ -45,7 +47,13 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev) 
	else

		speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)

			      >> OCOTP_CFG3_SPEED_GRADE_SHIFT;

	mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;



	if (of_machine_is_compatible("fsl,imx8mp"))

		mkt_segment = (cell_value & IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK)

			       >> IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT;

	else

		mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK)

			       >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;



	/*

	 * Early samples without fuses written report "0 0" which may NOT

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