drm/nouveau/mmu: convert to new-style nvkm_subdev (c9582455) · Commits · 戴 / test

drivers/gpu/drm/nouveau/include/nvif/device.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -52,7 +52,7 @@ u64 nvif_device_time(struct nvif_device *);
		})
		#define nvxx_bios(a) nvxx_device(a)->bios
		#define nvxx_fb(a) nvxx_device(a)->fb
		#define nvxx_mmu(a) nvkm_mmu(nvxx_device(a))
		#define nvxx_mmu(a) nvxx_device(a)->mmu
		#define nvxx_bar(a) nvxx_device(a)->bar
		#define nvxx_gpio(a) nvxx_device(a)->gpio
		#define nvxx_clk(a) nvxx_device(a)->clk

drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h

+15 −56

Original line number	Diff line number	Diff line
		@@ -39,62 +39,6 @@ struct nvkm_vm {
		u32 lpde;
		};

		struct nvkm_mmu {
		struct nvkm_subdev subdev;

		u64 limit;
		u8 dma_bits;
		u32 pgt_bits;
		u8 spg_shift;
		u8 lpg_shift;

		int (create)(struct nvkm_mmu , u64 offset, u64 length,
		u64 mm_offset, struct lock_class_key *,
		struct nvkm_vm **);

		void (map_pgt)(struct nvkm_gpuobj pgd, u32 pde,
		struct nvkm_memory *pgt[2]);
		void (map)(struct nvkm_vma , struct nvkm_memory *,
		struct nvkm_mem *, u32 pte, u32 cnt,
		u64 phys, u64 delta);
		void (map_sg)(struct nvkm_vma , struct nvkm_memory *,
		struct nvkm_mem , u32 pte, u32 cnt, dma_addr_t );
		void (unmap)(struct nvkm_vma , struct nvkm_memory *pgt,
		u32 pte, u32 cnt);
		void (flush)(struct nvkm_vm );
		};

		static inline struct nvkm_mmu *
		nvkm_mmu(void *obj)
		{
		return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MMU);
		}

		#define nvkm_mmu_create(p,e,o,i,f,d) \
		nvkm_subdev_create((p), (e), (o), 0, (i), (f), (d))
		#define nvkm_mmu_destroy(p) \
		nvkm_subdev_destroy(&(p)->subdev)
		#define nvkm_mmu_init(p) \
		nvkm_subdev_init_old(&(p)->subdev)
		#define nvkm_mmu_fini(p,s) \
		nvkm_subdev_fini_old(&(p)->subdev, (s))

		#define _nvkm_mmu_dtor _nvkm_subdev_dtor
		#define _nvkm_mmu_init _nvkm_subdev_init
		#define _nvkm_mmu_fini _nvkm_subdev_fini

		extern struct nvkm_oclass nv04_mmu_oclass;
		extern struct nvkm_oclass nv41_mmu_oclass;
		extern struct nvkm_oclass nv44_mmu_oclass;
		extern struct nvkm_oclass nv50_mmu_oclass;
		extern struct nvkm_oclass gf100_mmu_oclass;

		int nv04_vm_create(struct nvkm_mmu , u64, u64, u64, struct lock_class_key ,
		struct nvkm_vm **);
		void nv04_mmu_dtor(struct nvkm_object *);

		int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset,
		u32 block, struct lock_class_key , struct nvkm_vm *);
		int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset,
		struct lock_class_key , struct nvkm_vm *);
		int nvkm_vm_ref(struct nvkm_vm , struct nvkm_vm , struct nvkm_gpuobj pgd);
		@@ -106,4 +50,19 @@ void nvkm_vm_map(struct nvkm_vma , struct nvkm_mem );
		void nvkm_vm_map_at(struct nvkm_vma , u64 offset, struct nvkm_mem );
		void nvkm_vm_unmap(struct nvkm_vma *);
		void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length);

		struct nvkm_mmu {
		const struct nvkm_mmu_func *func;
		struct nvkm_subdev subdev;

		u64 limit;
		u8 dma_bits;
		u8 lpg_shift;
		};

		int nv04_mmu_new(struct nvkm_device , int, struct nvkm_mmu *);
		int nv41_mmu_new(struct nvkm_device , int, struct nvkm_mmu *);
		int nv44_mmu_new(struct nvkm_device , int, struct nvkm_mmu *);
		int nv50_mmu_new(struct nvkm_device , int, struct nvkm_mmu *);
		int gf100_mmu_new(struct nvkm_device , int, struct nvkm_mmu *);
		#endif

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+70 −70

Original line number	Diff line number	Diff line
		@@ -84,7 +84,7 @@ nv4_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -104,7 +104,7 @@ nv5_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -125,7 +125,7 @@ nv10_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -144,7 +144,7 @@ nv11_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -165,7 +165,7 @@ nv15_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -186,7 +186,7 @@ nv17_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -207,7 +207,7 @@ nv18_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -228,7 +228,7 @@ nv1a_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -249,7 +249,7 @@ nv1f_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -270,7 +270,7 @@ nv20_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -291,7 +291,7 @@ nv25_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -312,7 +312,7 @@ nv28_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -333,7 +333,7 @@ nv2a_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -354,7 +354,7 @@ nv30_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -375,7 +375,7 @@ nv31_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -397,7 +397,7 @@ nv34_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -419,7 +419,7 @@ nv35_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -440,7 +440,7 @@ nv36_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv04_instmem_new,
		.mc = nv04_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .timer = nv04_timer_new,
		// .disp = nv04_disp_new,
		// .dma = nv04_dma_new,
		@@ -462,7 +462,7 @@ nv40_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv40_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -487,7 +487,7 @@ nv41_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv40_mc_new,
		// .mmu = nv41_mmu_new,
		.mmu = nv41_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -512,7 +512,7 @@ nv42_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv40_mc_new,
		// .mmu = nv41_mmu_new,
		.mmu = nv41_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -537,7 +537,7 @@ nv43_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv40_mc_new,
		// .mmu = nv41_mmu_new,
		.mmu = nv41_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -562,7 +562,7 @@ nv44_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv44_mc_new,
		// .mmu = nv44_mmu_new,
		.mmu = nv44_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -587,7 +587,7 @@ nv45_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv40_mc_new,
		// .mmu = nv04_mmu_new,
		.mmu = nv04_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -612,7 +612,7 @@ nv46_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv44_mc_new,
		// .mmu = nv44_mmu_new,
		.mmu = nv44_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -637,7 +637,7 @@ nv47_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv40_mc_new,
		// .mmu = nv41_mmu_new,
		.mmu = nv41_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -662,7 +662,7 @@ nv49_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv40_mc_new,
		// .mmu = nv41_mmu_new,
		.mmu = nv41_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -687,7 +687,7 @@ nv4a_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv44_mc_new,
		// .mmu = nv44_mmu_new,
		.mmu = nv44_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -712,7 +712,7 @@ nv4b_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv40_mc_new,
		// .mmu = nv41_mmu_new,
		.mmu = nv41_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -737,7 +737,7 @@ nv4c_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv4c_mc_new,
		// .mmu = nv44_mmu_new,
		.mmu = nv44_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -762,7 +762,7 @@ nv4e_chipset = {
		.i2c = nv4e_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv4c_mc_new,
		// .mmu = nv44_mmu_new,
		.mmu = nv44_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -789,7 +789,7 @@ nv50_chipset = {
		.i2c = nv50_i2c_new,
		.imem = nv50_instmem_new,
		.mc = nv50_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .therm = nv50_therm_new,
		// .timer = nv04_timer_new,
		@@ -815,7 +815,7 @@ nv63_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv4c_mc_new,
		// .mmu = nv44_mmu_new,
		.mmu = nv44_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -840,7 +840,7 @@ nv67_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv4c_mc_new,
		// .mmu = nv44_mmu_new,
		.mmu = nv44_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -865,7 +865,7 @@ nv68_chipset = {
		.i2c = nv04_i2c_new,
		.imem = nv40_instmem_new,
		.mc = nv4c_mc_new,
		// .mmu = nv44_mmu_new,
		.mmu = nv44_mmu_new,
		// .therm = nv40_therm_new,
		// .timer = nv04_timer_new,
		// .volt = nv40_volt_new,
		@@ -892,7 +892,7 @@ nv84_chipset = {
		.i2c = nv50_i2c_new,
		.imem = nv50_instmem_new,
		.mc = nv50_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .therm = g84_therm_new,
		// .timer = nv04_timer_new,
		@@ -923,7 +923,7 @@ nv86_chipset = {
		.i2c = nv50_i2c_new,
		.imem = nv50_instmem_new,
		.mc = nv50_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .therm = g84_therm_new,
		// .timer = nv04_timer_new,
		@@ -954,7 +954,7 @@ nv92_chipset = {
		.i2c = nv50_i2c_new,
		.imem = nv50_instmem_new,
		.mc = nv50_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .therm = g84_therm_new,
		// .timer = nv04_timer_new,
		@@ -985,7 +985,7 @@ nv94_chipset = {
		.i2c = g94_i2c_new,
		.imem = nv50_instmem_new,
		.mc = g94_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .therm = g84_therm_new,
		// .timer = nv04_timer_new,
		@@ -1018,7 +1018,7 @@ nv96_chipset = {
		// .timer = nv04_timer_new,
		.fb = g84_fb_new,
		.imem = nv50_instmem_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		.bar = g84_bar_new,
		// .volt = nv40_volt_new,
		// .dma = nv50_dma_new,
		@@ -1049,7 +1049,7 @@ nv98_chipset = {
		// .timer = nv04_timer_new,
		.fb = g84_fb_new,
		.imem = nv50_instmem_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		.bar = g84_bar_new,
		// .volt = nv40_volt_new,
		// .dma = nv50_dma_new,
		@@ -1078,7 +1078,7 @@ nva0_chipset = {
		.i2c = nv50_i2c_new,
		.imem = nv50_instmem_new,
		.mc = g98_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .therm = g84_therm_new,
		// .timer = nv04_timer_new,
		@@ -1109,7 +1109,7 @@ nva3_chipset = {
		.i2c = g94_i2c_new,
		.imem = nv50_instmem_new,
		.mc = g98_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gt215_pmu_new,
		// .therm = gt215_therm_new,
		@@ -1142,7 +1142,7 @@ nva5_chipset = {
		.i2c = g94_i2c_new,
		.imem = nv50_instmem_new,
		.mc = g98_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gt215_pmu_new,
		// .therm = gt215_therm_new,
		@@ -1174,7 +1174,7 @@ nva8_chipset = {
		.i2c = g94_i2c_new,
		.imem = nv50_instmem_new,
		.mc = g98_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gt215_pmu_new,
		// .therm = gt215_therm_new,
		@@ -1206,7 +1206,7 @@ nvaa_chipset = {
		.i2c = g94_i2c_new,
		.imem = nv50_instmem_new,
		.mc = g98_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .therm = g84_therm_new,
		// .timer = nv04_timer_new,
		@@ -1237,7 +1237,7 @@ nvac_chipset = {
		.i2c = g94_i2c_new,
		.imem = nv50_instmem_new,
		.mc = g98_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .therm = g84_therm_new,
		// .timer = nv04_timer_new,
		@@ -1268,7 +1268,7 @@ nvaf_chipset = {
		.i2c = g94_i2c_new,
		.imem = nv50_instmem_new,
		.mc = g98_mc_new,
		// .mmu = nv50_mmu_new,
		.mmu = nv50_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gt215_pmu_new,
		// .therm = gt215_therm_new,
		@@ -1302,7 +1302,7 @@ nvc0_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gf100_ltc_new,
		.mc = gf100_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gf100_pmu_new,
		// .therm = gt215_therm_new,
		@@ -1337,7 +1337,7 @@ nvc1_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gf100_ltc_new,
		.mc = gf106_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gf100_pmu_new,
		// .therm = gt215_therm_new,
		@@ -1371,7 +1371,7 @@ nvc3_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gf100_ltc_new,
		.mc = gf106_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gf100_pmu_new,
		// .therm = gt215_therm_new,
		@@ -1405,7 +1405,7 @@ nvc4_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gf100_ltc_new,
		.mc = gf100_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gf100_pmu_new,
		// .therm = gt215_therm_new,
		@@ -1440,7 +1440,7 @@ nvc8_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gf100_ltc_new,
		.mc = gf100_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gf100_pmu_new,
		// .therm = gt215_therm_new,
		@@ -1475,7 +1475,7 @@ nvce_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gf100_ltc_new,
		.mc = gf100_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gf100_pmu_new,
		// .therm = gt215_therm_new,
		@@ -1510,7 +1510,7 @@ nvcf_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gf100_ltc_new,
		.mc = gf106_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gf100_pmu_new,
		// .therm = gt215_therm_new,
		@@ -1544,7 +1544,7 @@ nvd7_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gf100_ltc_new,
		.mc = gf106_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .therm = gf110_therm_new,
		// .timer = nv04_timer_new,
		@@ -1576,7 +1576,7 @@ nvd9_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gf100_ltc_new,
		.mc = gf106_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gf110_pmu_new,
		// .therm = gf110_therm_new,
		@@ -1610,7 +1610,7 @@ nve4_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gk104_ltc_new,
		.mc = gf106_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gk104_pmu_new,
		// .therm = gf110_therm_new,
		@@ -1646,7 +1646,7 @@ nve6_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gk104_ltc_new,
		.mc = gf106_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gk104_pmu_new,
		// .therm = gf110_therm_new,
		@@ -1682,7 +1682,7 @@ nve7_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gk104_ltc_new,
		.mc = gf106_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gf110_pmu_new,
		// .therm = gf110_therm_new,
		@@ -1714,7 +1714,7 @@ nvea_chipset = {
		.imem = gk20a_instmem_new,
		.ltc = gk104_ltc_new,
		.mc = gk20a_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .pmu = gk20a_pmu_new,
		// .timer = gk20a_timer_new,
		// .volt = gk20a_volt_new,
		@@ -1742,7 +1742,7 @@ nvf0_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gk104_ltc_new,
		.mc = gf106_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gk110_pmu_new,
		// .therm = gf110_therm_new,
		@@ -1778,7 +1778,7 @@ nvf1_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gk104_ltc_new,
		.mc = gf106_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gk110_pmu_new,
		// .therm = gf110_therm_new,
		@@ -1814,7 +1814,7 @@ nv106_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gk104_ltc_new,
		.mc = gk20a_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gk208_pmu_new,
		// .therm = gf110_therm_new,
		@@ -1849,7 +1849,7 @@ nv108_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gk104_ltc_new,
		.mc = gk20a_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gk208_pmu_new,
		// .therm = gf110_therm_new,
		@@ -1884,7 +1884,7 @@ nv117_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gm107_ltc_new,
		.mc = gk20a_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gk208_pmu_new,
		// .therm = gm107_therm_new,
		@@ -1913,7 +1913,7 @@ nv124_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gm107_ltc_new,
		.mc = gk20a_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gk208_pmu_new,
		// .timer = gk20a_timer_new,
		@@ -1942,7 +1942,7 @@ nv126_chipset = {
		.imem = nv50_instmem_new,
		.ltc = gm107_ltc_new,
		.mc = gk20a_mc_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .mxm = nv50_mxm_new,
		// .pmu = gk208_pmu_new,
		// .timer = gk20a_timer_new,
		@@ -1967,8 +1967,8 @@ nv12b_chipset = {
		.imem = gk20a_instmem_new,
		.ltc = gm107_ltc_new,
		.mc = gk20a_mc_new,
		// .mmu = gf100_mmu_new,
		// .mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		.mmu = gf100_mmu_new,
		// .timer = gk20a_timer_new,
		// .ce[2] = gm204_ce2_new,
		// .dma = gf119_dma_new,

drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c

+0 −9

Original line number	Diff line number	Diff line
		@@ -31,7 +31,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
		@@ -50,7 +49,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
		@@ -69,7 +67,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
		@@ -87,7 +84,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
		@@ -106,7 +102,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
		@@ -124,7 +119,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
		@@ -142,7 +136,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
		@@ -161,7 +154,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
		@@ -179,7 +171,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c

+0 −8

Original line number	Diff line number	Diff line
		@@ -31,7 +31,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
		@@ -51,7 +50,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
		@@ -71,7 +69,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
		@@ -89,7 +86,6 @@ gk104_identify(struct nvkm_device *device)
		break;
		case 0xea:
		device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
		@@ -103,7 +99,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
		@@ -123,7 +118,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
		@@ -143,7 +137,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
		@@ -162,7 +155,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;

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