Commit c955cd2b authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update IvyBridge events to V20 



Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/20180118234518.GA27753@tassilo.jf.intel.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 032c16b2

tools/perf/pmu-events/arch/x86/ivybridge/cache.json

+111 −456

File changed.

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tools/perf/pmu-events/arch/x86/ivybridge/frontend.json

+61 −61
Original line number Diff line number Diff line
@@ -20,76 +20,45 @@ 
        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x8",

        "EventName": "IDQ.DSB_UOPS",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x10",

        "EventName": "IDQ.MS_DSB_UOPS",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x20",

        "EventName": "IDQ.MS_MITE_UOPS",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",

        "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x30",

        "EventName": "IDQ.MS_UOPS",

        "UMask": "0x4",

        "EventName": "IDQ.MITE_CYCLES",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",

        "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x30",

        "EventName": "IDQ.MS_CYCLES",

        "UMask": "0x8",

        "EventName": "IDQ.DSB_UOPS",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "CounterMask": "1",

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",

        "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x4",

        "EventName": "IDQ.MITE_CYCLES",

        "UMask": "0x8",

        "EventName": "IDQ.DSB_CYCLES",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x8",

        "EventName": "IDQ.DSB_CYCLES",

        "UMask": "0x10",

        "EventName": "IDQ.MS_DSB_UOPS",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

        "CounterMask": "1",

        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {
@@ -137,6 +106,16 @@ 
        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x20",

        "EventName": "IDQ.MS_MITE_UOPS",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",

        "EventCode": "0x79",
@@ -159,6 +138,39 @@ 
        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x30",

        "EventName": "IDQ.MS_UOPS",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x30",

        "EventName": "IDQ.MS_CYCLES",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x30",

        "EdgeDetect": "1",

        "EventName": "IDQ.MS_SWITCHES",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Number of uops delivered to IDQ from any path.",

        "EventCode": "0x79",
@@ -289,17 +301,5 @@ 
        "SampleAfterValue": "2000003",

        "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",

        "EventCode": "0x79",

        "Counter": "0,1,2,3",

        "UMask": "0x30",

        "EdgeDetect": "1",

        "EventName": "IDQ.MS_SWITCHES",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    }

]
 
 No newline at end of file

tools/perf/pmu-events/arch/x86/ivybridge/memory.json

+10 −82
Original line number Diff line number Diff line
@@ -37,18 +37,6 @@ 
        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PEBS": "2",

        "EventCode": "0xCD",

        "Counter": "3",

        "UMask": "0x2",

        "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",

        "PRECISE_STORE": "1",

        "TakenAlone": "1",

        "CounterHTOff": "3"

    },

    {

        "PEBS": "2",

        "PublicDescription": "Loads with latency value being above 4.",
@@ -162,75 +150,15 @@ 
        "CounterHTOff": "3"

    },

    {

        "EventCode": "0xB7, 0xBB",

        "MSRValue": "0x300400244",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "Offcore": "1",

        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",

        "SampleAfterValue": "100003",

        "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xB7, 0xBB",

        "MSRValue": "0x300400091",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "Offcore": "1",

        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",

        "SampleAfterValue": "100003",

        "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xB7, 0xBB",

        "MSRValue": "0x3004003f7",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "Offcore": "1",

        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",

        "SampleAfterValue": "100003",

        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xB7, 0xBB",

        "MSRValue": "0x300400004",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "Offcore": "1",

        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",

        "SampleAfterValue": "100003",

        "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xB7, 0xBB",

        "MSRValue": "0x300400001",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "Offcore": "1",

        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",

        "SampleAfterValue": "100003",

        "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xB7, 0xBB",

        "MSRValue": "0x6004001b3",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "Offcore": "1",

        "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",

        "MSRIndex": "0x1a6,0x1a7",

        "SampleAfterValue": "100003",

        "BriefDescription": "Counts LLC replacements",

        "CounterHTOff": "0,1,2,3"

        "PEBS": "2",

        "EventCode": "0xCD",

        "Counter": "3",

        "UMask": "0x2",

        "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",

        "PRECISE_STORE": "1",

        "TakenAlone": "1",

        "CounterHTOff": "3"

    }

]
 
 No newline at end of file

tools/perf/pmu-events/arch/x86/ivybridge/other.json

+10 −10
Original line number Diff line number Diff line
@@ -9,16 +9,6 @@ 
        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",

        "EventCode": "0x5C",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "EventName": "CPL_CYCLES.RING123",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.",

        "EventCode": "0x5C",
@@ -31,6 +21,16 @@ 
        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",

        "EventCode": "0x5C",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "EventName": "CPL_CYCLES.RING123",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",

        "EventCode": "0x63",

tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json

+412 −410

File changed.

Preview size limit exceeded, changes collapsed.

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