Commit c934878c authored Nov 06, 2009 by Uwe Kleine-König Committed by Greg Kroah-Hartman Dec 11, 2009

Serial: pxa: work around Errata #75



Intel(R) PXA27x Processor Family Specification Update (Nov 2005)
says:

  E75. UART: Baud rate may not be programmed correctly on
       back-to-back writes.

  Problem:
  When programming the Divisor Latch registers, Low and High (DLL and
  DLH), with back-to-back writes, the second register write may not
  take effect. The result is an incorrect baud rate.

  Workaround:
  After programming the first Divisor Latch register, read and verify
  it before programming the second Divisor Latch register.

This was hit when changing the baud rate from 115200 to 9600 while
receiving characters at 9600 Bd.

And fixed indention of some comments nearby.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

parent 4c0ebb80

drivers/serial/pxa.c

+11 −2

Original line number	Diff line number	Diff line
		@@ -438,6 +438,7 @@ serial_pxa_set_termios(struct uart_port port, struct ktermios termios,
		unsigned char cval, fcr = 0;
		unsigned long flags;
		unsigned int baud, quot;
		unsigned int dll;

		switch (termios->c_cflag & CSIZE) {
		case CS5:
		@@ -536,6 +537,14 @@ serial_pxa_set_termios(struct uart_port port, struct ktermios termios,

		serial_out(up, UART_LCR, cval \| UART_LCR_DLAB); /* set DLAB */
		serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */

		/*
		* work around Errata #75 according to Intel(R) PXA27x Processor Family
		* Specification Update (Nov 2005)
		*/
		dll = serial_in(up, UART_DLL);
		WARN_ON(dll != (quot & 0xff));

		serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
		serial_out(up, UART_LCR, cval); /* reset DLAB */
		up->lcr = cval; /* Save LCR */

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