Commit c93240a7 authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update Skylake events to V36 



Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/20180118234518.GA27753@tassilo.jf.intel.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent ffaa6f27

tools/perf/pmu-events/arch/x86/skylake/cache.json

+515 −3875

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tools/perf/pmu-events/arch/x86/skylake/floating-point.json

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@@ -27,7 +27,6 @@ 
        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "EventCode": "0xC7",

        "Counter": "0,1,2,3",

        "UMask": "0x8",
@@ -55,7 +54,7 @@ 
        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",

        "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",

        "EventCode": "0xCA",

        "Counter": "0,1,2,3",

        "UMask": "0x1e",

tools/perf/pmu-events/arch/x86/skylake/frontend.json

+121 −111

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tools/perf/pmu-events/arch/x86/skylake/memory.json

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tools/perf/pmu-events/arch/x86/skylake/other.json

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[

    {

        "PublicDescription": "This event counts the number of hardware interruptions received by the processor.",

        "EventCode": "0x32",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "SW_PREFETCH_ACCESS.NTA",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of PREFETCHNTA instructions executed.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x32",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "EventName": "SW_PREFETCH_ACCESS.T0",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of PREFETCHT0 instructions executed.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x32",

        "Counter": "0,1,2,3",

        "UMask": "0x4",

        "EventName": "SW_PREFETCH_ACCESS.T1_T2",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x32",

        "Counter": "0,1,2,3",

        "UMask": "0x8",

        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of PREFETCHW instructions executed.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Counts the number of hardware interruptions received by the processor.",

        "EventCode": "0xCB",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "HW_INTERRUPTS.RECEIVED",

        "SampleAfterValue": "100003",

        "SampleAfterValue": "203",

        "BriefDescription": "Number of hardware interrupts received by the processor.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    }

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