Commit c90dec00 authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
Browse files

ARM: imx: add i.mx6ulz msl support 



The i.MX 6ULZ processor is a high-performance, ultra
cost-efficient consumer Linux processor featuring an
advanced implementation of a single Arm® Cortex®-A7 core,
which operates at speeds up to 900 MHz.

This patch adds basic MSL support for i.MX6ULZ, the
i.MX6ULZ has same soc_id as i.MX6ULL, and SRC_SBMR2 bit[6]
is to differentiate i.MX6ULZ from i.MX6ULL, 1'b1 means
i.MX6ULZ and 1'b0 means i.MX6ULL.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 8148d213

arch/arm/mach-imx/anatop.c

+20 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
#define ANADIG_DIGPROG_IMX6SL	0x280

#define ANADIG_DIGPROG_IMX7D	0x800



#define SRC_SBMR2		0x1c



#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG	0x40000

#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN	0x8

#define BM_ANADIG_REG_CORE_FET_ODRIVE		0x20000000
@@ -148,6 +150,24 @@ void __init imx_init_revision_from_anatop(void) 
		major_part = (digprog >> 8) & 0xf;

		minor_part = digprog & 0xf;

		revision = ((major_part + 1) << 4) | minor_part;



		if ((digprog >> 16) == MXC_CPU_IMX6ULL) {

			void __iomem *src_base;

			u32 sbmr2;



			np = of_find_compatible_node(NULL, NULL,

						     "fsl,imx6ul-src");

			src_base = of_iomap(np, 0);

			WARN_ON(!src_base);

			sbmr2 = readl_relaxed(src_base + SRC_SBMR2);

			iounmap(src_base);



			/* src_sbmr2 bit 6 is to identify if it is i.MX6ULZ */

			if (sbmr2 & (1 << 6)) {

				digprog &= ~(0xff << 16);

				digprog |= (MXC_CPU_IMX6ULZ << 16);

			}

		}

	}



	mxc_set_cpu_type(digprog >> 16 & 0xff);

arch/arm/mach-imx/cpu.c

+3 −0
Original line number Diff line number Diff line
@@ -136,6 +136,9 @@ struct device * __init imx_soc_device_init(void) 
	case MXC_CPU_IMX6ULL:

		soc_id = "i.MX6ULL";

		break;

	case MXC_CPU_IMX6ULZ:

		soc_id = "i.MX6ULZ";

		break;

	case MXC_CPU_IMX6SLL:

		soc_id = "i.MX6SLL";

		break;

arch/arm/mach-imx/mxc.h

+7 −0
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ 
#define MXC_CPU_IMX6Q		0x63

#define MXC_CPU_IMX6UL		0x64

#define MXC_CPU_IMX6ULL		0x65

/* virtual cpu id for i.mx6ulz */

#define MXC_CPU_IMX6ULZ		0x6b

#define MXC_CPU_IMX6SLL		0x67

#define MXC_CPU_IMX7D		0x72
@@ -80,6 +82,11 @@ static inline bool cpu_is_imx6ull(void) 
	return __mxc_cpu_type == MXC_CPU_IMX6ULL;

}



static inline bool cpu_is_imx6ulz(void)

{

	return __mxc_cpu_type == MXC_CPU_IMX6ULZ;

}



static inline bool cpu_is_imx6sll(void)

{

	return __mxc_cpu_type == MXC_CPU_IMX6SLL;

arch/arm/mach-imx/pm-imx6.c

+2 −2
Original line number Diff line number Diff line
@@ -313,7 +313,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) 
		if (cpu_is_imx6sl())

			val |= BM_CLPCR_BYPASS_PMIC_READY;

		if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||

		    cpu_is_imx6ull() || cpu_is_imx6sll())

		    cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())

			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;

		else

			val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
@@ -331,7 +331,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) 
		if (cpu_is_imx6sl() || cpu_is_imx6sx())

			val |= BM_CLPCR_BYPASS_PMIC_READY;

		if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||

		    cpu_is_imx6ull() || cpu_is_imx6sll())

		    cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())

			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;

		else

			val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;

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