Commit c8e9627d authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Add a name for the Punit GPLLENABLE bit 



Remove the magic number for the GPLLENABLE bit by adding a name for it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDeepak <S&lt;deepak.s@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 9a3b9c7a

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -576,6 +576,7 @@ enum punit_power_well { 
#define PUNIT_REG_GPU_LFM			0xd3

#define PUNIT_REG_GPU_FREQ_REQ			0xd4

#define PUNIT_REG_GPU_FREQ_STS			0xd8

#define   GPLLENABLE				(1<<4)

#define   GENFREQSTATUS				(1<<0)

#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc

#define PUNIT_REG_CZ_TIMESTAMP			0xce

drivers/gpu/drm/i915/intel_pm.c

+2 −2
Original line number Diff line number Diff line
@@ -5333,7 +5333,7 @@ static void cherryview_enable_rps(struct drm_device *dev) 


	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);



	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");

	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");

	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);



	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
@@ -5413,7 +5413,7 @@ static void valleyview_enable_rps(struct drm_device *dev) 


	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);



	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");

	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");

	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);



	dev_priv->rps.cur_freq = (val >> 8) & 0xff;

CRA Git | Maintained and supported by SUSTech CRA and CCSE