Commit c8df9a53 authored Apr 29, 2008 by Linus Walleij Committed by Russell King May 04, 2008

[ARM] 5024/1: Fix some minor clk issues in the MMCI PL18x driver

This fixes some two minor clk issues.

The first is a comparison where a byte will probably wrap around to 0 instead of being saturated to 255, shouldn't be triggered very often but need fixing.

The second is an attempt by the driver to adjust MCLK down to the maximum frequency according to the spec, so we don't accidentally overclock the PL18x block. None of the mach-{versatile|integrator|lh7a40x} that use it in-tree seem to have a problem with this (all are well below 100MHz, typically 33MHz), but some day there will be a problem.

This is not applied on top of the earlier mmci patch for race condition but rather a clean 2.6.25, but I guess it applies without major protests anyway.

Signed-off-by: Linus Walleij <triad@df.lth.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent f8b6389b

drivers/mmc/host/mmci.c

+13 −1

Original line number	Diff line number	Diff line
		@@ -425,7 +425,7 @@ static void mmci_set_ios(struct mmc_host mmc, struct mmc_ios ios)
		host->cclk = host->mclk;
		} else {
		clk = host->mclk / (2 * ios->clock) - 1;
		if (clk > 256)
		if (clk >= 256)
		clk = 255;
		host->cclk = host->mclk / (2 * (clk + 1));
		}
		@@ -512,6 +512,18 @@ static int mmci_probe(struct amba_device dev, void id)

		host->plat = plat;
		host->mclk = clk_get_rate(host->clk);
		/*
		* According to the spec, mclk is max 100 MHz,
		* so we try to adjust the clock down to this,
		* (if possible).
		*/
		if (host->mclk > 100000000) {
		ret = clk_set_rate(host->clk, 100000000);
		if (ret < 0)
		goto clk_disable;
		host->mclk = clk_get_rate(host->clk);
		DBG(host, "eventual mclk rate: %u Hz\n", host->mclk);
		}
		host->mmc = mmc;
		host->base = ioremap(dev->res.start, SZ_4K);
		if (!host->base) {

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