Commit c856052a authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira Committed by Rodrigo Vivi
Browse files

drm/i915: Remove ddi_pll_sel from intel_crtc_state 



The value of ddi_pll_sel is derived from the selection of shared dpll,
so just calculate the final value when necessary.

v2: Actually remove it from crtc state and delete remaining usages. (CI)

Reviewed-by: default avatarDurgadoss R <durgadoss.r@intel.com>
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent dfa10480

drivers/gpu/drm/i915/intel_ddi.c

+34 −11
Original line number Diff line number Diff line
@@ -546,6 +546,27 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 
	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));

}



static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)

{

	switch (pll->id) {

	case DPLL_ID_WRPLL1:

		return PORT_CLK_SEL_WRPLL1;

	case DPLL_ID_WRPLL2:

		return PORT_CLK_SEL_WRPLL2;

	case DPLL_ID_SPLL:

		return PORT_CLK_SEL_SPLL;

	case DPLL_ID_LCPLL_810:

		return PORT_CLK_SEL_LCPLL_810;

	case DPLL_ID_LCPLL_1350:

		return PORT_CLK_SEL_LCPLL_1350;

	case DPLL_ID_LCPLL_2700:

		return PORT_CLK_SEL_LCPLL_2700;

	default:

		MISSING_CASE(pll->id);

		return PORT_CLK_SEL_NONE;

	}

}



/* Starting with Haswell, different DDI ports can work in FDI mode for

 * connection to the PCH-located connectors. For this, it is necessary to train

 * both the DDI port and PCH receiver for the desired DDI buffer settings.
@@ -561,7 +582,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) 
	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_encoder *encoder;

	u32 temp, i, rx_ctl_val;

	u32 temp, i, rx_ctl_val, ddi_pll_sel;



	for_each_encoder_on_crtc(dev, crtc, encoder) {

		WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
@@ -592,8 +613,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) 
	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);



	/* Configure Port Clock Select */

	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);

	WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);

	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(intel_crtc->config->shared_dpll);

	I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);

	WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);



	/* Start the training iterating through available voltages and emphasis,

	 * testing each value twice. */
@@ -870,7 +892,7 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder, 
	int link_clock = 0;

	uint32_t dpll_ctl1, dpll;



	dpll = pipe_config->ddi_pll_sel;

	dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);



	dpll_ctl1 = I915_READ(DPLL_CTRL1);
@@ -918,7 +940,7 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder, 
	int link_clock = 0;

	u32 val, pll;



	val = pipe_config->ddi_pll_sel;

	val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);

	switch (val & PORT_CLK_SEL_MASK) {

	case PORT_CLK_SEL_LCPLL_810:

		link_clock = 81000;
@@ -1586,13 +1608,15 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp) 
}



void intel_ddi_clk_select(struct intel_encoder *encoder,

			  const struct intel_crtc_state *pipe_config)

			  struct intel_shared_dpll *pll)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum port port = intel_ddi_get_encoder_port(encoder);



	if (WARN_ON(!pll))

		return;



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		uint32_t dpll = pipe_config->ddi_pll_sel;

		uint32_t val;



		/* DDI -> PLL mapping  */
@@ -1600,14 +1624,13 @@ void intel_ddi_clk_select(struct intel_encoder *encoder, 


		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |

			DPLL_CTRL2_DDI_CLK_SEL_MASK(port));

		val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |

		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |

			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));



		I915_WRITE(DPLL_CTRL2, val);



	} else if (INTEL_INFO(dev_priv)->gen < 9) {

		WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);

		I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);

		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));

	}

}
@@ -1632,7 +1655,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder, 
		intel_edp_panel_on(intel_dp);

	}



	intel_ddi_clk_select(intel_encoder, crtc->config);

	intel_ddi_clk_select(intel_encoder, crtc->config->shared_dpll);



	if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {

		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/intel_display.c

+8 −35
Original line number Diff line number Diff line
@@ -10435,15 +10435,12 @@ static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, 


	switch (port) {

	case PORT_A:

		pipe_config->ddi_pll_sel = SKL_DPLL0;

		id = DPLL_ID_SKL_DPLL0;

		break;

	case PORT_B:

		pipe_config->ddi_pll_sel = SKL_DPLL1;

		id = DPLL_ID_SKL_DPLL1;

		break;

	case PORT_C:

		pipe_config->ddi_pll_sel = SKL_DPLL2;

		id = DPLL_ID_SKL_DPLL2;

		break;

	default:
@@ -10462,25 +10459,10 @@ static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, 
	u32 temp;



	temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);

	pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);

	id = temp >> (port * 3 + 1);



	switch (pipe_config->ddi_pll_sel) {

	case SKL_DPLL0:

		id = DPLL_ID_SKL_DPLL0;

		break;

	case SKL_DPLL1:

		id = DPLL_ID_SKL_DPLL1;

		break;

	case SKL_DPLL2:

		id = DPLL_ID_SKL_DPLL2;

		break;

	case SKL_DPLL3:

		id = DPLL_ID_SKL_DPLL3;

		break;

	default:

		MISSING_CASE(pipe_config->ddi_pll_sel);

	if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))

		return;

	}



	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);

}
@@ -10490,10 +10472,9 @@ static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, 
				struct intel_crtc_state *pipe_config)

{

	enum intel_dpll_id id;

	uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));



	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));



	switch (pipe_config->ddi_pll_sel) {

	switch (ddi_pll_sel) {

	case PORT_CLK_SEL_WRPLL1:

		id = DPLL_ID_WRPLL1;

		break;
@@ -10513,7 +10494,7 @@ static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, 
		id = DPLL_ID_LCPLL_2700;

		break;

	default:

		MISSING_CASE(pipe_config->ddi_pll_sel);

		MISSING_CASE(ddi_pll_sel);

		/* fall through */

	case PORT_CLK_SEL_NONE:

		return;
@@ -12797,10 +12778,9 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, 
	DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);



	if (IS_BROXTON(dev)) {

		DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"

		DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"

			      "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "

			      "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",

			      pipe_config->ddi_pll_sel,

			      pipe_config->dpll_hw_state.ebb0,

			      pipe_config->dpll_hw_state.ebb4,

			      pipe_config->dpll_hw_state.pll0,
@@ -12813,15 +12793,13 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, 
			      pipe_config->dpll_hw_state.pll10,

			      pipe_config->dpll_hw_state.pcsdw12);

	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {

		DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "

		DRM_DEBUG_KMS("dpll_hw_state: "

			      "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",

			      pipe_config->ddi_pll_sel,

			      pipe_config->dpll_hw_state.ctrl1,

			      pipe_config->dpll_hw_state.cfgcr1,

			      pipe_config->dpll_hw_state.cfgcr2);

	} else if (HAS_DDI(dev)) {

		DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",

			      pipe_config->ddi_pll_sel,

		DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",

			      pipe_config->dpll_hw_state.wrpll,

			      pipe_config->dpll_hw_state.spll);

	} else {
@@ -12930,7 +12908,6 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) 
	struct intel_crtc_scaler_state scaler_state;

	struct intel_dpll_hw_state dpll_hw_state;

	struct intel_shared_dpll *shared_dpll;

	uint32_t ddi_pll_sel;

	bool force_thru;



	/* FIXME: before the switch to atomic started, a new pipe_config was
@@ -12942,7 +12919,6 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) 
	scaler_state = crtc_state->scaler_state;

	shared_dpll = crtc_state->shared_dpll;

	dpll_hw_state = crtc_state->dpll_hw_state;

	ddi_pll_sel = crtc_state->ddi_pll_sel;

	force_thru = crtc_state->pch_pfit.force_thru;



	memset(crtc_state, 0, sizeof *crtc_state);
@@ -12951,7 +12927,6 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) 
	crtc_state->scaler_state = scaler_state;

	crtc_state->shared_dpll = shared_dpll;

	crtc_state->dpll_hw_state = dpll_hw_state;

	crtc_state->ddi_pll_sel = ddi_pll_sel;

	crtc_state->pch_pfit.force_thru = force_thru;

}
@@ -13374,8 +13349,6 @@ intel_pipe_config_compare(struct drm_device *dev, 


	PIPE_CONF_CHECK_I(double_wide);



	PIPE_CONF_CHECK_X(ddi_pll_sel);



	PIPE_CONF_CHECK_P(shared_dpll);

	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);

	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);

drivers/gpu/drm/i915/intel_dp_mst.c

+2 −1
Original line number Diff line number Diff line
@@ -150,7 +150,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, 
	DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);



	if (intel_dp->active_mst_links == 0) {

		intel_ddi_clk_select(&intel_dig_port->base, pipe_config);

		intel_ddi_clk_select(&intel_dig_port->base,

				     pipe_config->shared_dpll);



		intel_prepare_dp_ddi_buffers(&intel_dig_port->base);

		intel_dp_set_link_params(intel_dp,

drivers/gpu/drm/i915/intel_dpll_mgr.c

+0 −27
Original line number Diff line number Diff line
@@ -452,26 +452,6 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, 
	return val & SPLL_PLL_ENABLE;

}



static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)

{

	switch (pll->id) {

	case DPLL_ID_WRPLL1:

		return PORT_CLK_SEL_WRPLL1;

	case DPLL_ID_WRPLL2:

		return PORT_CLK_SEL_WRPLL2;

	case DPLL_ID_SPLL:

		return PORT_CLK_SEL_SPLL;

	case DPLL_ID_LCPLL_810:

		return PORT_CLK_SEL_LCPLL_810;

	case DPLL_ID_LCPLL_1350:

		return PORT_CLK_SEL_LCPLL_1350;

	case DPLL_ID_LCPLL_2700:

		return PORT_CLK_SEL_LCPLL_2700;

	default:

		return PORT_CLK_SEL_NONE;

	}

}



#define LC_FREQ 2700

#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
@@ -751,8 +731,6 @@ hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 
	if (!pll)

		return NULL;



	crtc_state->ddi_pll_sel = hsw_pll_to_ddi_pll_sel(pll);



	intel_reference_shared_dpll(pll, crtc_state);



	return pll;
@@ -1274,8 +1252,6 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 
	if (!pll)

		return NULL;



	crtc_state->ddi_pll_sel = pll->id;



	intel_reference_shared_dpll(pll, crtc_state);



	return pll;
@@ -1628,9 +1604,6 @@ bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 


	intel_reference_shared_dpll(pll, crtc_state);



	/* shared DPLL id 0 is DPLL A */

	crtc_state->ddi_pll_sel = pll->id;



	return pll;

}

drivers/gpu/drm/i915/intel_drv.h

+1 −7
Original line number Diff line number Diff line
@@ -590,12 +590,6 @@ struct intel_crtc_state { 
	/* Selected dpll when shared or NULL. */

	struct intel_shared_dpll *shared_dpll;



	/*

	 * - PORT_CLK_SEL for DDI ports on HSW/BDW.

	 * - enum skl_dpll on SKL

	 */

	uint32_t ddi_pll_sel;



	/* Actual register state of the dpll, for shared dpll cross-checking. */

	struct intel_dpll_hw_state dpll_hw_state;
@@ -1136,7 +1130,7 @@ void intel_crt_reset(struct drm_encoder *encoder); 


/* intel_ddi.c */

void intel_ddi_clk_select(struct intel_encoder *encoder,

			  const struct intel_crtc_state *pipe_config);

			  struct intel_shared_dpll *pll);

void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,

				struct intel_crtc_state *old_crtc_state,

				struct drm_connector_state *old_conn_state);

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