Commit c84e1efa authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'asm-generic-fixes-5.10-2' of... 

Merge tag 'asm-generic-fixes-5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic

Pull asm-generic fix from Arnd Bergmann:
 "Add correct MAX_POSSIBLE_PHYSMEM_BITS setting to asm-generic.

  This is a single bugfix for a bug that Stefan Agner found on 32-bit
  Arm, but that exists on several other architectures"

* tag 'asm-generic-fixes-5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic:
  arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where needed
parents 303bc934 cef39703

arch/arc/include/asm/pgtable.h

+2 −0
Original line number Diff line number Diff line
@@ -134,8 +134,10 @@ 


#ifdef CONFIG_ARC_HAS_PAE40

#define PTE_BITS_NON_RWX_IN_PD1	(0xff00000000 | PAGE_MASK | _PAGE_CACHEABLE)

#define MAX_POSSIBLE_PHYSMEM_BITS 40

#else

#define PTE_BITS_NON_RWX_IN_PD1	(PAGE_MASK | _PAGE_CACHEABLE)

#define MAX_POSSIBLE_PHYSMEM_BITS 32

#endif



/**************************************************************************

arch/arm/include/asm/pgtable-2level.h

+2 −0
Original line number Diff line number Diff line
@@ -75,6 +75,8 @@ 
#define PTE_HWTABLE_OFF		(PTE_HWTABLE_PTRS * sizeof(pte_t))

#define PTE_HWTABLE_SIZE	(PTRS_PER_PTE * sizeof(u32))



#define MAX_POSSIBLE_PHYSMEM_BITS	32



/*

 * PMD_SHIFT determines the size of the area a second-level page table can map

 * PGDIR_SHIFT determines what a third-level page table entry can map

arch/arm/include/asm/pgtable-3level.h

+2 −0
Original line number Diff line number Diff line
@@ -25,6 +25,8 @@ 
#define PTE_HWTABLE_OFF		(0)

#define PTE_HWTABLE_SIZE	(PTRS_PER_PTE * sizeof(u64))



#define MAX_POSSIBLE_PHYSMEM_BITS 40



/*

 * PGDIR_SHIFT determines the size a top-level page table entry can map.

 */

arch/mips/include/asm/pgtable-32.h

+3 −0
Original line number Diff line number Diff line
@@ -154,6 +154,7 @@ static inline void pmd_clear(pmd_t *pmdp) 


#if defined(CONFIG_XPA)



#define MAX_POSSIBLE_PHYSMEM_BITS 40

#define pte_pfn(x)		(((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))

static inline pte_t

pfn_pte(unsigned long pfn, pgprot_t prot)
@@ -169,6 +170,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) 


#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)



#define MAX_POSSIBLE_PHYSMEM_BITS 36

#define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))



static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
@@ -183,6 +185,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 


#else



#define MAX_POSSIBLE_PHYSMEM_BITS 32

#ifdef CONFIG_CPU_VR41XX

#define pte_pfn(x)		((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))

#define pfn_pte(pfn, prot)	__pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))

arch/powerpc/include/asm/book3s/32/pgtable.h

+2 −0
Original line number Diff line number Diff line
@@ -36,8 +36,10 @@ static inline bool pte_user(pte_t pte) 
 */

#ifdef CONFIG_PTE_64BIT

#define PTE_RPN_MASK	(~((1ULL << PTE_RPN_SHIFT) - 1))

#define MAX_POSSIBLE_PHYSMEM_BITS 36

#else

#define PTE_RPN_MASK	(~((1UL << PTE_RPN_SHIFT) - 1))

#define MAX_POSSIBLE_PHYSMEM_BITS 32

#endif



/*

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