Commit c84ad0d6 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: update odm mode validation to be in line with policy 



Previously 8k30 worked with dsc and odm combine due to a workaround that ran
the formula a second time with dsc support enable should dsc validation fail.
This worked when clocks were low enough for formula to enable odm to lower
voltage, however now broke due to increased clocks.

This change updates the ODM combine policy within the formula to properly
reflect our current policy within DC, only enabling ODM when we have to, as
well as adding a check for viewport width when dsc is enabled.

As a side effect the redundant call to dml when odm is required is now
unnecessary.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarNikola Cornij <Nikola.Cornij@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3a4d180d

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+1 −21
Original line number Diff line number Diff line
@@ -2248,11 +2248,7 @@ bool dcn20_fast_validate_bw( 
	bool out = false;



	int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;

	bool odm_capable = context->bw_ctx.dml.ip.odm_capable;

	bool force_split = false;

#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

	bool failed_non_odm_dsc = false;

#endif

	int split_threshold = dc->res_pool->pipe_count / 2;

	bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
@@ -2329,22 +2325,6 @@ bool dcn20_fast_validate_bw( 
		goto validate_out;

	}



	context->bw_ctx.dml.ip.odm_capable = 0;



	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);



	context->bw_ctx.dml.ip.odm_capable = odm_capable;



#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

	/* 1 dsc per stream dsc validation */

	if (vlevel <= context->bw_ctx.dml.soc.num_states)

		if (!dcn20_validate_dsc(dc, context)) {

			failed_non_odm_dsc = true;

			vlevel = context->bw_ctx.dml.soc.num_states + 1;

		}

#endif



	if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)

	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);



	if (vlevel > context->bw_ctx.dml.soc.num_states)
@@ -2482,7 +2462,7 @@ bool dcn20_fast_validate_bw( 
	}

#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

	/* Actual dsc count per stream dsc validation*/

	if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) {

	if (!dcn20_validate_dsc(dc, context)) {

		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =

				DML_FAIL_DSC_VALIDATION_FAILURE;

		goto validate_fail;

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

+8 −1
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 


#define BPP_INVALID 0

#define BPP_BLENDED_PIPE 0xffffffff

#define DCN20_MAX_DSC_IMAGE_WIDTH 5184



static double adjust_ReturnBW(

		struct display_mode_lib *mode_lib,
@@ -3901,6 +3902,10 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode 
				mode_lib->vba.MaximumSwathWidthInLineBuffer);

	}

	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {

		double MaxMaxDispclkRoundedDown = RoundToDFSGranularityDown(

			mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states],

			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);



		for (j = 0; j < 2; j++) {

			mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(

				mode_lib->vba.MaxDispclk[i],
@@ -3925,7 +3930,9 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode 
						&& i == mode_lib->vba.soc.num_states)

					mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2

							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);

				if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {

				if (mode_lib->vba.ODMCapability == false ||

						(locals->PlaneRequiredDISPCLKWithoutODMCombine <= MaxMaxDispclkRoundedDown

							&& (!locals->DSCEnabled[k] || locals->HActive[k] <= DCN20_MAX_DSC_IMAGE_WIDTH))) {

					locals->ODMCombineEnablePerState[i][k] = false;

					mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;

				} else {

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