drm/amd/sriov skip vcn powergating and dec_ring_test (c8466cc0) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -421,6 +421,10 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
		unsigned i;
		int r;

		/* VCN in SRIOV does not support direct register read/write */
		if (amdgpu_sriov_vf(adev))
		return 0;

		WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
		r = amdgpu_ring_alloc(ring, 3);
		if (r)

+16 −5

Original line number	Diff line number	Diff line
		@@ -354,11 +354,13 @@ static int vcn_v3_0_hw_fini(void *handle)

		ring = &adev->vcn.inst[i].ring_dec;

		if (!amdgpu_sriov_vf(adev)) {
		if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) \|\|
		(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
		RREG32_SOC15(VCN, i, mmUVD_STATUS)))
		RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
		vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);

		}
		}
		ring->sched.ready = false;

		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
		@@ -1861,6 +1863,15 @@ static int vcn_v3_0_set_powergating_state(void *handle,
		struct amdgpu_device adev = (struct amdgpu_device )handle;
		int ret;

		/* for SRIOV, guest should not control VCN Power-gating
		* MMSCH FW should control Power-gating and clock-gating
		* guest should avoid touching CGC and PG
		*/
		if (amdgpu_sriov_vf(adev)) {
		adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
		return 0;
		}

		if(state == adev->vcn.cur_state)
		return 0;