MIPS: Loongson-3: Enable Store Fill Buffer at runtime (c824ad16) · Commits · 戴 / test

New Loongson-3 (Loongson-3A R2, Loongson-3A R3, and newer) has SFB (Store Fill Buffer) which can improve the performance of memory access. Now, SFB enablement is controlled by CONFIG_LOONGSON3_ENHANCEMENT, and the generic kernel has no benefit from SFB (even it is running on a new Loongson-3 machine). With this patch, we can enable SFB at runtime by detecting the CPU type (the expense is war_io_reorder_wmb() will always be a 'sync', which will hurt the performance of old Loongson-3). [paul.burton@mips.com: Further info from Huacai: In practise, I found that sometimes there are boot failures if I enable SFB/LPA in cpu_probe(). I don't know why because processor designers also haven't give me an explaination, but I think this may have some relationships to speculative execution.] Signed-off-by:

Huacai Chen <chenhc@lemote.com> Signed-off-by:

Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20426/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>

arch/mips/include/asm/io.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -289,7 +289,7 @@ static inline void iounmap(const volatile void __iomem *addr)
		#undef __IS_KSEG1
		}

		#if defined(CONFIG_CPU_CAVIUM_OCTEON) \|\| defined(CONFIG_LOONGSON3_ENHANCEMENT)
		#if defined(CONFIG_CPU_CAVIUM_OCTEON) \|\| defined(CONFIG_CPU_LOONGSON3)
		#define war_io_reorder_wmb() wmb()
		#else
		#define war_io_reorder_wmb() barrier()

arch/mips/include/asm/mach-loongson64/kernel-entry-init.h

+12 −4

Original line number	Diff line number	Diff line
		@@ -11,6 +11,8 @@
		#ifndef __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
		#define __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H

		#include <asm/cpu.h>

		/*
		* Override macros used in arch/mips/kernel/head.S.
		*/
		@@ -26,12 +28,15 @@
		mfc0 t0, CP0_PAGEGRAIN
		or t0, (0x1 << 29)
		mtc0 t0, CP0_PAGEGRAIN
		#ifdef CONFIG_LOONGSON3_ENHANCEMENT
		/* Enable STFill Buffer */
		mfc0 t0, CP0_PRID
		andi t0, (PRID_IMP_MASK \| PRID_REV_MASK)
		slti t0, (PRID_IMP_LOONGSON_64 \| PRID_REV_LOONGSON3A_R2)
		bnez t0, 1f
		mfc0 t0, CP0_CONFIG6
		or t0, 0x100
		mtc0 t0, CP0_CONFIG6
		#endif
		1:
		_ehb
		.set pop
		#endif
		@@ -52,12 +57,15 @@
		mfc0 t0, CP0_PAGEGRAIN
		or t0, (0x1 << 29)
		mtc0 t0, CP0_PAGEGRAIN
		#ifdef CONFIG_LOONGSON3_ENHANCEMENT
		/* Enable STFill Buffer */
		mfc0 t0, CP0_PRID
		andi t0, (PRID_IMP_MASK \| PRID_REV_MASK)
		slti t0, (PRID_IMP_LOONGSON_64 \| PRID_REV_LOONGSON3A_R2)
		bnez t0, 1f
		mfc0 t0, CP0_CONFIG6
		or t0, 0x100
		mtc0 t0, CP0_CONFIG6
		#endif
		1:
		_ehb
		.set pop
		#endif

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